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5,801 Views
Registered: ‎06-04-2016

Synthesis failed vivado 2015.4

I tried synthesising the block design shown in the attachment, got the following errors

 

CRITICAL WARNING: [IP_Flow 19-663] Failed to copy file 'd:/hwswcodesignvivado/ip_repo/edit_finaltryaxi_v1_0.srcs/sources_1/new/finalmul.v', it does not exist.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'processingsystem_finaltryaxi_0_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'processingsystem_finaltryaxi_0_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block finaltryaxi_0

 

How to fix this issue ???

 

Thanks in advance

Anuroop

 

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3 Replies
Moderator
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5,800 Views
Registered: ‎01-16-2013

Re: Synthesis failed vivado 2015.4

anuroop.ekm@gmail.com,

 

What is this file and does this exist in the specified location?

d:/hwswcodesignvivado/ip_repo/edit_finaltryaxi_v1_0.srcs/sources_1/new/finalmul.v'

 

Can you try to reset the output products of Block Design and regenerate them?Capture.PNG

 

 

--Syed

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5,770 Views
Registered: ‎06-04-2016

Re: Synthesis failed vivado 2015.4

Even after regenerating the output products same errors persists. There is no such file in the specified location. It is a 16-bit multiplier. I am trying to access this multiplier using AXI interface, from PS. For that, I created a user IP with AXI lite and multiplier logic( Verilog ). Thanks for the reply ..

 

..Anuroop

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5,756 Views
Registered: ‎06-04-2016

Re: Synthesis failed vivado 2015.4

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