06-29-2016 02:43 AM
I tried synthesising the block design shown in the attachment, got the following errors
CRITICAL WARNING: [IP_Flow 19-663] Failed to copy file 'd:/hwswcodesignvivado/ip_repo/edit_finaltryaxi_v1_0.srcs/sources_1/new/finalmul.v', it does not exist.
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'processingsystem_finaltryaxi_0_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'processingsystem_finaltryaxi_0_0'. Failed to generate 'Verilog Synthesis' outputs:
ERROR: [BD 41-1030] Generation failed for the IP Integrator block finaltryaxi_0
How to fix this issue ???
Thanks in advance
06-29-2016 02:45 AM - edited 06-29-2016 02:49 AM
What is this file and does this exist in the specified location?
Can you try to reset the output products of Block Design and regenerate them?
06-29-2016 09:28 AM
Even after regenerating the output products same errors persists. There is no such file in the specified location. It is a 16-bit multiplier. I am trying to access this multiplier using AXI interface, from PS. For that, I created a user IP with AXI lite and multiplier logic( Verilog ). Thanks for the reply ..