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Observer george_mrch
Observer
168 Views
Registered: ‎01-29-2018

System Synchronous data transmission

I'm using a simple test project to test the connection between the FPGAs. The frequency of my project is 250 MHz. In the forward direction the data is transmitted without errors, but in the reverse direction some bits are returned damaged. The clock signal lines up to each FPGA have the same length. The input and output triggers of the launch/latch trigger are packed in the IOB. Can I use set_input/output delay and not place the corrupted bit registers in the IOB so that the tool can place triggers to meet the project timing requirements? Can I receive data on the negative edge of the clock signal for the corrupted bits? What can I do in this situation?

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3 Replies
Scholar drjohnsmith
Scholar
164 Views
Registered: ‎07-09-2009

Re: System Synchronous data transmission

lots of questions here
first up, have you seen this
https://www.xilinx.com/products/intellectual-property/axi-chip2chip.html

can you draw up a block diagram please
what do you mean by trigger

Are you sending clock from both FPGAs to the other

Is the data bus single or bi directional

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Observer george_mrch
Observer
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Registered: ‎01-29-2018

Re: System Synchronous data transmission

The watch comes from the High-Performance Clock Buffer on the board. I simply send data from one FPGA to another. There they unfold to be transferred back. The data buses are unidirectional.

Untitled Diagram.png
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Scholar drjohnsmith
Scholar
115 Views
Registered: ‎07-09-2009

Re: System Synchronous data transmission

OK
are you using the MMCM in each device ? these will help zero out some of the delays / skews to the same,
what do you mean by watch and high performance buffer?

The track length of the clock to the two fpgas in this scheem need to be matched to the same electrical length

You will also need to force the IO registers into the IOB,

Do I assume you have no clock nor IO timing constraints, At 100 Mhz you are probably going to get away without constraints, but at 250 Mhz, they are going to be essential

You are also going to need your bus between the two chips to be all equal lengths and proper termination at the ends if its more than a few cm long,

The normal way of doing this, would be to send the clock with the the data , over the same matched length tracks, Then the receiver has a guaranteed set up / hold time , then using a clock crossing circuit in each fpga to re align the data to the internal clock








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