10-21-2019 02:46 AM
I'm using a simple test project to test the connection between the FPGAs. The frequency of my project is 250 MHz. In the forward direction the data is transmitted without errors, but in the reverse direction some bits are returned damaged. The clock signal lines up to each FPGA have the same length. The input and output triggers of the launch/latch trigger are packed in the IOB. Can I use set_input/output delay and not place the corrupted bit registers in the IOB so that the tool can place triggers to meet the project timing requirements? Can I receive data on the negative edge of the clock signal for the corrupted bits? What can I do in this situation?
10-21-2019 02:56 AM
10-21-2019 03:30 AM
The watch comes from the High-Performance Clock Buffer on the board. I simply send data from one FPGA to another. There they unfold to be transferred back. The data buses are unidirectional.
10-21-2019 05:45 AM