04-08-2021 06:33 AM
I've got a 4 DACs that all share a clock line. The data lines and clock are LVCMOS33, FAST slew rate, and drive strength 12.
I am seeing glitches on one of the DACs (the one closest to the clock line FPGA pin), if I have the farthest DAC connected to the clock line. The the farthest DAC is disconnected, there are no glitches. If I put a termination resistor to GND near the far DAC I can get rid of the glitches. I've tested resistor values down to 150 ohms, and between 150 and 333 ohms all work.
My question is, what termination resistors are "allowed?" What are the relevant specs? I understand that LVCMOS does not require termination normally, but there seems to be some kind of impedance effect happening on the circuitboard that is leading to reflections or distortion near the one DAC.
I wasn't exactly sure how to interpret the drive strength attribute. 3.3V and 12 mA corresponds to a 275 ohm impedance, but does that mean that I am out of spec if I drive a <275 ohm load?
Thanks for the help.
04-08-2021 10:07 AM
I would suggest a signal integrity simulation to check the signal quality with your board's stack up with different resistor values. Generally for the LVCMOS series resistance is used. In the simulation, there should not be any ringing. If the ringing is crossing the noise margin, then that will result in glitches.
Based on the simulation result, you can decide the best resistor value.
If simulation is not possible, then capture the clock signal using oscilloscope & see whether there is any ringing. Then, by experimenting with different resistor values, decide the best termination values which will remove the ringing to the acceptable level.
If the board is impedance controlled & the clock routing impedance is 50ohm, then a 22ohm to 33 ohm series resistor should give a good signal quality.
04-08-2021 10:25 AM
Interesting, I was not aware that series resistance was typical on LVCMOS. The board is not impedance controlled. A 100 ohm series resistor is enough to get rid of the glitches. I'll so some more empirical investigation along these lines.... We might have a scope with high enough speed to see ringing on a 200 MHz clock.... I unfortunately do not have the time, resources, or skills to so a signal integrity simulation.
04-08-2021 11:08 AM
This might be a useful pointer to termination
The other thing to keep in mind, is reflections of the ends of the traces,
if you routed dac a to dac b to dac c to dac D , then you will have a better signal than if you had made a christmas tree type routing,
Also may be an obvious, the DACs are going to be clocked at different times as they are at different distances down the track,
which depending what your doing with the DACs may or may not be a problem,
Generally, its a good lesson to learn, 200 MHz clock needs to be routed in a controlled impedance way,
04-08-2021 11:28 AM
Thanks for this info. I did the "christmas tree" routing because I figured it would be simpler to meet timing with the single clock. I will definitely keep controlled impedance routing in the list for future projects....
Interestingly It looks like having a 10-100 ohm series resistors on all 4 clock inputs works. I'm probably going to stick with 25 on all of them for now, to have margin, and see how the noise is.
04-08-2021 11:37 AM
your into the lucky design technique there,