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2,190 Views
Registered: ‎05-18-2017

Test Basys 3 board with Vivado 2017.1

I wanted to test the Basys 3 board received from Xilinx with Vivado 2017.1. is there any tutorials available that I can use to test the board to make sure it works fine with Vivado 2017.1?

 

t

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3 Replies
Scholar austin
Scholar
2,177 Views
Registered: ‎02-27-2008

Re: Test Basys 3 board with Vivado 2017.1

f,

 

If it didn't work, 2017.1 would have failed the "normal use test."

 

Of course it "works" with 2017.1.  Just open hardware manager, and look at the XADC for temperature and voltages.  It will communicate with the Artix device on the board and "work" just fine.

 

Note that the instructional materials (labs for courses) are keyed to specific versions.  Do not expect a different version of Vivado to work with designs not matching (different versions).  Vivado is neither forward nor backward compatible, so with any different version, all warnings must be reviewed, all errors cleared, and functionality re-verified for any design.

 

So there is "works as in programs and talks to, and there is "works" as in compatibility with different versions.  This first is assured, the latter not.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar u4223374
Scholar
2,114 Views
Registered: ‎04-26-2015

Re: Test Basys 3 board with Vivado 2017.1

You don't need to test the board with Vivado 2017.1 specifically; if the board works, and if Vivado 2017.1 works, then they'll work together.

 

It's like testing a PC and a monitor. If the PC works, and the monitor works, then they'll work together. The connection is standardized, so as long as they both meet the standard there's no real need to test them together.

 

Do the Basys 3 tutorials using whatever version of Vivado those are written for. Once you're convinced that the board is working, feel free to switch over to 2017.1.

 

 

 

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2,022 Views
Registered: ‎05-26-2015

Re: Test Basys 3 board with Vivado 2017.1

I would not recommend 2017.1 for the basys 3 board. Programming the boot rom is a bit sketchy. See the referenced thread on the acknowledged bug.

https://forums.xilinx.com/t5/Design-Methodologies-and/2017-1-Configuration-Memory-Programming-Bug/td-p/763803

 

I got it to program by including the prm file ( as suggested in the post) , and also turning on bitstream compression. I use a tcl script run prior to "generate bitstream", by selecting it in the project options. This script turns on compression, and generates the mcs file.

 

2017.1 has a nicer interface, and finally fixes a bug in the editor's column mode, so it is worth using. You might want to keep a copy of 2016.4 lab tools around just for programming in case you run into issues.

 

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