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Observer
Observer
5,152 Views
Registered: ‎09-04-2014

Test Bench Error

I am trying to get a test bench up and running and I get these errors i don't understand.  there is no prevent_reg_update

 

ERROR: [VRFC 10-704] formal prevent_reg_update has no actual or default value [C:/Users/xxxxxx/Documents/control monitor/modified/project_3/project_3.srcs/sources_1/imports/temp/regifile_fsk_test.vhd:26]


ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit cm_fpga_10 in library work failed.

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Xilinx Employee
Xilinx Employee
5,146 Views
Registered: ‎08-02-2011

What does line 26 of regifile_fsk_test.vhd look like?
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Observer
Observer
5,144 Views
Registered: ‎09-04-2014

Prevent_reg_update : in std_logic; -- Allows writing to all registers

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Xilinx Employee
Xilinx Employee
5,127 Views
Registered: ‎08-02-2011

Have you tried searching for the error message? A few min on google gives some useful advice.

http://stackoverflow.com/questions/14527201/vhdl-assigning-default-values

"All entity inputs must have either a signal driving them, or a default value specified in the entity declaration."
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