08-11-2015 12:24 PM
I am trying to get a test bench up and running and I get these errors i don't understand. there is no prevent_reg_update
ERROR: [VRFC 10-704] formal prevent_reg_update has no actual or default value [C:/Users/xxxxxx/Documents/control monitor/modified/project_3/project_3.srcs/sources_1/imports/temp/regifile_fsk_test.vhd:26]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit cm_fpga_10 in library work failed.
08-11-2015 01:03 PM