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Explorer
Explorer
3,941 Views
Registered: ‎04-13-2013

The max lut utilization in 7 series

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hi

  I have used spartan6 devices for many years.According to experience,the lut utilization in spartan6 is 75%.otherwize the place and route is very hard and it is hard to archieve the timing closure.

so my question is what the max lut utilization in 7 series is.

Michael

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Thanks for god,I meet FPGA.
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Xilinx Employee
Xilinx Employee
6,707 Views
Registered: ‎09-05-2007

Re: The max lut utilization in 7 series

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For what it's worth here's the 'Slice Logic' utilisation report for my latest design in an XC7S50 Spartan-7 device...

 

1. Slice Logic

--------------

 

+------------------------+-------+-------+-----------+-------+

| Site Type              | Used  | Fixed | Available | Util% |

+------------------------+-------+-------+-----------+-------+

| Slice LUTs             | 30185 |     0 |     32600 | 92.59 |

| LUT as Logic           | 25449 |     0 |     32600 | 78.06 |

| LUT as Memory          |  4736 |     0 |      9600 | 49.33 |

| LUT as Distributed RAM |  3552 |     0 |           |       |

| LUT as Shift Register  |  1184 |     0 |           |       |

| Slice Registers        | 29069 |     0 |     65200 | 44.58 |

| Register as Flip Flop  | 29069 |     0 |     65200 | 44.58 |

| Register as Latch      |     0 |     0 |     65200 |  0.00 |

| F7 Muxes               |   751 |     0 |     16300 |  4.61 |

| F8 Muxes               |     8 |     0 |      8150 |  0.10 |

+------------------------+-------+-------+-----------+-------+

 

By the way, it also uses 100% of the BRAMs.

 

No issues implementing the design.

 

 

Ken Chapman
Principal Engineer, Xilinx UK

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6 Replies
Moderator
Moderator
3,933 Views
Registered: ‎11-09-2015

Re: The max lut utilization in 7 series

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Hi @haitaox,

 

It is the same in 7-series devices. Refer to UG949:

 

UF.JPG

 

Regards,

 

Florent

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar u4223374
Scholar
3,908 Views
Registered: ‎04-26-2015

Re: The max lut utilization in 7 series

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Vivado generally does a better job than ISE did, so if you're switching tools as well as switching devices then you'll see some improvement. I've seen 7-series designs pass timing with well over 80% of LUTs used, some pushing up towards 90% (not sure that we ever actually reached 90%, it's been a while). Obviously the 7-series fabric is a bit quicker too, so if you're aiming for the same clock speed then you'll find timing closure easier.

Explorer
Explorer
3,895 Views
Registered: ‎04-13-2013

Re: The max lut utilization in 7 series

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hi @florentw

  in ug949,it is silce utilization.I mean lut utilization.

  in my old design,the silce utilization is always above 99%,even 100%

Michael

------------------------------------------
Thanks for god,I meet FPGA.
------------------------------------------
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Explorer
Explorer
3,894 Views
Registered: ‎04-13-2013

Re: The max lut utilization in 7 series

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hi, @u4223374

thanks to your reply,it is a good news to me

Michael

------------------------------------------
Thanks for god,I meet FPGA.
------------------------------------------
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Xilinx Employee
Xilinx Employee
6,708 Views
Registered: ‎09-05-2007

Re: The max lut utilization in 7 series

Jump to solution

For what it's worth here's the 'Slice Logic' utilisation report for my latest design in an XC7S50 Spartan-7 device...

 

1. Slice Logic

--------------

 

+------------------------+-------+-------+-----------+-------+

| Site Type              | Used  | Fixed | Available | Util% |

+------------------------+-------+-------+-----------+-------+

| Slice LUTs             | 30185 |     0 |     32600 | 92.59 |

| LUT as Logic           | 25449 |     0 |     32600 | 78.06 |

| LUT as Memory          |  4736 |     0 |      9600 | 49.33 |

| LUT as Distributed RAM |  3552 |     0 |           |       |

| LUT as Shift Register  |  1184 |     0 |           |       |

| Slice Registers        | 29069 |     0 |     65200 | 44.58 |

| Register as Flip Flop  | 29069 |     0 |     65200 | 44.58 |

| Register as Latch      |     0 |     0 |     65200 |  0.00 |

| F7 Muxes               |   751 |     0 |     16300 |  4.61 |

| F8 Muxes               |     8 |     0 |      8150 |  0.10 |

+------------------------+-------+-------+-----------+-------+

 

By the way, it also uses 100% of the BRAMs.

 

No issues implementing the design.

 

 

Ken Chapman
Principal Engineer, Xilinx UK

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Explorer
Explorer
3,832 Views
Registered: ‎04-13-2013

Re: The max lut utilization in 7 series

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Hi, @chapman

    First thank you so much for your reply!

    The LUT utilization is above 90% in your design.

    It is so good,and much better than spartan6.

   

 

   By the way,I love your picoblaze!

Michael

------------------------------------------
Thanks for god,I meet FPGA.
------------------------------------------
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