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Adventurer
Adventurer
222 Views
Registered: ‎12-19-2018

Timing error on unused DSP48E1 inputs

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Hello Xilinx Community,

I'm facing an issue using a DSP48E1 block on an Artix 7 device.

Despite the fact that everything works well on hardware, I'm getting a timing error after implementation that I don't fully understand.

Let me give you some background first.

 

I'm multiplying 2 signed values (5bits and 16 bits) each clock cycle (fclk = 200MHz).

I've used the Xilinx Multiplier IP core for this purpose (Vivado 2019.2).

 

While all data paths related to the LSBs are ok for timing, I do see the MSB register of the input value is connected to all unused / remaining inputs of the DSP48E1 (e.g. up to input 25).

All these inputs from the same register are giving timing errors in the range of -0.3ns.

I assume this linked to the fact that I'm using signed multiplication?

 

The main question is - is there any better way of doing this or any workaround to solve this issue?

 

Thanks, best regards,

SC

 

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bruce_karaffa
Scholar
Scholar
216 Views
Registered: ‎06-21-2017

200MHz is not very fast for a 7 series DSP.  How many cycles of latency are you using?  Can you add another latency cycle?  I don't know why the sign extension would give the router problems but it looks like it is.

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bruce_karaffa
Scholar
Scholar
217 Views
Registered: ‎06-21-2017

200MHz is not very fast for a 7 series DSP.  How many cycles of latency are you using?  Can you add another latency cycle?  I don't know why the sign extension would give the router problems but it looks like it is.

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Adventurer
Adventurer
207 Views
Registered: ‎12-19-2018

Hi @bruce_karaffa ,

 

Thanks for the quick reply.

Currently the latency is set to 1 - I'll try to increase to 3.

From what i can see on the timing report and the routing,, the main issue is that all the MSBs up to 25 are driven by the same register, while the lower bits are driven by their individual data register.

 

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