01-26-2018 07:09 AM
my task is to read out an image sensor and store the images in memory. The only part that troubles me are the timings of the interface and how to best design the input interface of the FPGA. The sensor is an Onsemi MT9P006 (datasheet) which operates at 96 MHz with a 2.8 V power supply. The FPGA that reads out the images is an Artix-7 which will be soon replaced with an Zynq 7030. For some reasons I'm not allowed to use IP blocks and have to build the design with the primitives directly.
The datasheet suggests to capture the data, FV and LV signals on the falling edge of the pixel clock (p.28) but the timings show that the FV and LV signals can be too late for an 96 MHz clock. My first idea was to use an IDELAY for input pixel clock. Other ideas would be to use an MMCM and shift the phase by -90° or to sample the input with double the frequency and with an ISERDES and choose the sample from the correct quadrant.
Which one of these would be the best to capture the input pixels?
Thanks in advance,
01-26-2018 07:57 AM
At a rough look at the datasheet, it looks like you can safely capture the data using the falling edge of the pixel clock, and you can capture the LV and FV signals using the rising edge. You shouldn't be worried about being able to capture this data, 96 Mhz is pretty darn slow compared to a lot of other IO data problems.
01-26-2018 12:51 PM
Very good idea, thanks. This would only need an IDDR to sample the data at the falling edge and LV and FV at the next rising edge which results in a simpler design. I'm still unsure if the clock should go to a PLL or directly to an BUFR. Does this need a PLL? Also does the IDDR still need a synchronizer?
01-26-2018 12:54 PM
Try a BUFR first. There should be no need for a synchronizer.