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Registered: ‎01-17-2019

Timing ignore constraint (UCF) for asynchronous data into flip flop

Hi,

I am currently designing for a virtex 6 on ISE 14.6 an serial data recovery unit. The data is sampled asynchronously by a 8 phases 90 Mhz clock. My design pass the PAR timing analysis with not any timing issue.

In my testbench as this is my main goal I feed a flip flop input with a data signal that is totally asynchronous with the flip flop clock (the data signal is the output of an IDELAYE1) and when i simulation thourgh ISIM of course I have HOLD violation and setup violation. All of this is perfectly normal and does not represent a design mis function. That's why I would like to make ISIM ignore those violation and not displaying any error message while running the simulation.

So a small diagram would be :

 

DATA_IN ----> IDELAYE1-> DATA_DELAYED -> FLIP_FLOP -> DATA_FLIPFLOPPED

I tried to create a TIG in the UCF on the signal DATA_DELAYED.
This signal is with the KEEP attribute in my design.
I used the following entry :

NET "DATA_DELAYED" TIG

No problem during the translation state the command is correctly understood by ISE, but i keep having the hold violation issue displayed during simulation.
What am I missing here in the UCF file ?

Thank you,

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Registered: ‎09-17-2018

Re: Timing ignore constraint (UCF) for asynchronous data into flip flop

In ISE,

Data crossing clock domains is ignored by default.  It the two clocks are related, then you can create a constraint.  If the clocks are asynchronous, any clock constraint is meaningless, and should not be there.  In the synchronizer itself, you should have a max delay constraint between the DFF that samples the data Q, and the syncronizer stage DDFF D pin that is in the receiving clock domain (the data crossing 'to' domain clock).

In Vivado, all clocks are considered related, and a TIG (timing ignore) constraint is required for asynchronous data crossings between two clock domains.  

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Registered: ‎01-17-2019

Re: Timing ignore constraint (UCF) for asynchronous data into flip flop

The data is not crossing any clock domain internally. The data input comes from the outside world (IOB) through the IDELAYE1 and then is sampled by the first DFF.

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Registered: ‎09-17-2018

Re: Timing ignore constraint (UCF) for asynchronous data into flip flop

That is a data crossing clock domains.

Are you saying you have no clock for the data?  All you do is sample a data bit?

In which case, there is no other constraint to make.  All you need to do is figure out what the newly sampled data is.

 

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