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Visitor ydohi
Visitor
4,290 Views
Registered: ‎12-12-2009

Transceiver Wizard - How generate C/QPLLREEFCLKSEL port?

HI,

 

I'm trying to make GTX transceiver with various REFCLK inputs, using "7 Series FPGAs Transceiver Wizard".
Page 2 of 7 on Wizard requires REFCLK connection geometry, and generated .xco has no C/QPLLREFCLKSEL ports, though it has 7 REFCLK ports for each PLL. (GT0_GTGREFCLK_IN, GT0_GTNORTHREFCLK0_IN, etc.)
Without setting REFCLK geometry, Wizard shows error and generates no .xco.

 

Page2of7onWizard

Page 2 of 7 on Wizard 

 

 

noREFCLKSELport

no REFCLKSEL port, even 7 REFCLK input ports exist(in instance template file) 

 

 

Can't I use Wizard for these application?
Should I instantiate GTX2_COMMON & GTX2_CHANNEL primitives? (It's quite troublesome!)
If so, where can I get GTX2_COMMON & GTX2_CHANNEL library guide?

 

 

--Wizard ver2.6, ISE ver14.6 (running on lin64)
--device Kintex7 XC7K235T (on KC742 board)

 

Thank you all.
DOHI

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3 Replies
Xilinx Employee
Xilinx Employee
4,211 Views
Registered: ‎07-23-2012

Re: Transceiver Wizard - How generate C/QPLLREEFCLKSEL port?

Hi,

 

A value is directly assigned to the ports CPLLREFCLKSEL änd QPLLREFCLKSEL in the top level file of the tranceiver core. 

 

If you would want to modify the CPLLREFCLK, you can follow one of the two steps given below-

 

1) Re-customize the 7-series Transceiver core to select the correct source for CPLL.

2) Instead of adding the .xco, manually add the vhdl or verliog files and then modify the values.

 

If you are looking to change the value on the fly, define CPLLREFCLKSEL as an input port and bring it to top level.

 

Regards,

Krishna 

-----------------------------------------------------------------------------------------------
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Visitor ydohi
Visitor
4,198 Views
Registered: ‎12-12-2009

Re: Transceiver Wizard - How generate C/QPLLREEFCLKSEL port?

Hi, 

 

Thank you for replying.

Now I'm trying the way 1) you suggested.

 

 

 

 

Anyway, I found out 2 wrapper files in "ipcore_dir" directory. "transmit.vhd" and "transmit_gt.vhd"

(transmit is module name I gave.)

"GTXE2_COMMON" and 4 "transmit_gt"s are instantiated in "transmit.vhd"

and

1 GTXE2_CHANNEL is instantiated in "transmit_gt.vhd".

 

Port QPLLREFCLKSEL of GTXE2_COMMON is mapped as "001"

and port CPLLREFCLKSEL of GTXE_CHANNEL is mapped as "001".

It's same if I use Verilog.

It's meaning QPLL and all channel CPLLs are selected REFCLK0 regardless of Wizard setting.

 

When removing "Advanced Clocking Option" CHECK on Wizard to try,

the same structured wrapper files were generated.

It's meaning all channel are selected the same REFCLK regardless of Wizard setting.

 

It's necessary to rewrite wrapper files whenever assign to each channel a separate REFCLK.

 

Does anyone know directory of gtwizard2.6 release note?

 

Thank you all,

DOHI

 

 

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Visitor ydohi
Visitor
4,163 Views
Registered: ‎12-12-2009

Re: Transceiver Wizard - How generate C/QPLLREEFCLKSEL port?

I fond out release note
AR# 56454 http://www.xilinx.com/support/answers/56454.html
but no issue about this.

DOHI
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