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Registered: ‎11-23-2016

Translate fails after applying keep attribute on IO buffer input signal

I have a design targeted on Spartan 6 XC6SLX25-3FGG484. This design has a microprocessor data bus which is a bidirectional bus and i have the bus declared as inout on top level entity. When i try to add the input signals of the IO buffer on Chipscope ILA, they are not visible on Chipscope inserter. To prevent ISE from trimming away the IO buffer input signal, i tried applying "keep" attribute on the input signal. However applying "keep" attribute on input signal caused translate step in Implement to fail.

 

To troubleshoot the translate issue, and to rule out anything in my larger project, i made a very small project to test only one io buffer and found the translate fails even on the small IO buffer test project.

 

The errors observed in translate are copied below-

 

------------------------------------------------------------------------------------------

Annotating constraints to design from ucf file
"C:/Users/Sameer/FTEB/IOBUFTEST/Source/FTEB.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <NET "HOST_D" LOC = "P20" |>
[C:/Users/Sameer/FTEB/IOBUFTEST/Source/FTEB.ucf(4)]: NET "HOST_D" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "HOST_D" LOC = "P20" |>
[C:/Users/Sameer/FTEB/IOBUFTEST/Source/FTEB.ucf(4)]' could not be found and
so the Locate constraint will be removed.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;>
[C:/Users/Sameer/FTEB/IOBUFTEST/Source/FTEB.ucf(4)]: NET "HOST_D" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

Done...

------------------------------------------------------------------------------------------

 

The content of the IOBUFTEST. VHDL and UCF files are copied below

 

-----------------------------------------------------------------------------------------------

------------------ Content of IO Buffer test VHDL file ------------------------------

------------------------------------------------------------------------------------------------

 


Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_signed.all;

library UNISIM;

Library WORK;
--use WORK.FPGA_PACKAGE.ALL;
use UNISIM.VComponents.all;

entity IOBUFTEST is
Port (
HOST_D : inout std_logic;
PROC_READ : in std_logic
);
attribute keep : string;
attribute keep of IOBUFTEST : entity is "true";
end IOBUFTEST;


architecture IOBUFTEST_behav of IOBUFTEST is

signal HOST_D_D0 : std_logic; -- Sameer 12JUN2018
signal HOST_D_INT : std_logic; -- Sameer 12JUN2018

attribute keep of HOST_D_D0 : signal is "true";

begin


-------------------------------------------------------------------------------
----------- Bidirectional data bus interfacing MPC860 Microprocessor ----------
-------------------------------------------------------------------------------

HOST_D <= HOST_D_INT when (PROC_READ = '0') else 'Z';
HOST_D_D0 <= HOST_D;


end IOBUFTEST_behav;

 

---- End of VHDL source file

-------------------------------------------------------------------------------------------------------------

-------------------------------------- Content of UCF file --------------------------------------------

-------------------------------------------------------------------------------------------------------------

 

# Written by: Xilinx XPort Language Converter, Version 4.1 (110)
# Date: 13-Oct-2017 05:51 PM

NET "HOST_D" LOC = "P20" | IOSTANDARD = LVTTL;

NET "PROC_READ" LOC = "T3" | IOSTANDARD = LVTTL;

 

---- End of UCF file

 

--------------------------------------------------------------------------------------------------------------

 

If i comment out the attribute keep of HOST_D_D0 : signal is "true"; before begin in the above VHDL code, then translate passes and ISE can generate programming file. However in the larger project, the input signals gets trimmed away and i'm unable to view on Chipscope.

 

What should be done to resolve the translate fail problem?

 

Another question - Is there any way other than applying "keep" attribute to prevent ISE from trimming away the signals and view the IO buffer signals on Chipscope ILA?

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jheslip
Xilinx Employee
Xilinx Employee
690 Views
Registered: ‎06-30-2010

If you instantiate an IOBUF instead does that work.

 

You can find the template on page 132: https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf

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