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chao_xilinx
Visitor
Visitor
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Registered: ‎01-23-2019

UG936 Vivado tutorial programming debugging, the three IP file sine_high.xci sine_mid.xci sine_low.xci cannot be used.

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When I working on the UG936 Lab 1, after synthesis it says 3 black box, implying the 3 IP cannot be linked properly.

I notice the it has the message below shown in the graphs. Can you help me how I can use it?

ip_issue.PNG

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chao_xilinx
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Registered: ‎01-23-2019

Hi Chinmay,

Yes, this resolve the issue.

Thanks

View solution in original post

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chinmays
Xilinx Employee
Xilinx Employee
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Registered: ‎06-27-2018

 Hi @chao_xilinx,

Which version of Vivado are you using? Also, what error are you exactly getting? Run report_ip_status from gui or tcl console and if you get upgrade IP option there, upgrade the IP and rerun the implementation (I guess synthesis must have completed). Please let me know if this resolves the issue.

Thanks,

Chinmay 

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chao_xilinx
Visitor
Visitor
622 Views
Registered: ‎01-23-2019

Hi Chinmay,

Yes, this resolve the issue.

Thanks

View solution in original post

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