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Contributor
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Registered: ‎06-05-2010

Ultrascale GTH clock scheme recommendation

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I'm hoping to get some advice on a clocking scheme using the Ultrascale GTH.  Attached is a block diagram I hope can be used as a reference.

 

This is a 10Ge low latency application.  I'm using the async tx and rx gearboxes and avoiding FIFOs.  I'm also using the rx and tx Programmable dividers configured to divide by 16.5.  So far so good.  To avoid FIFOs I'm thinking of using the recovered clock for both RXUSRCLK, TXUSRCLK, and the User Clock.  Theoretically this would put everything on the same clock domain, but this is where I'm hoping for some feedback/advice.

 

I'm trying to figure out if the BUFG_GT can really drive user logic directly as implied by some figures in UG576.  If not then I guess I need a variation to this scheme.  Can someone offer some advice please?

 

Also, I haven't used a recovered clock before like this so I'm wondering what happens when the fiber is connected and disconnected.  I believe I need to detect this and reset some things, just not exactly sure which and in what order.  Advice on this would also be appreciated.  

 

Thanks,

Mike

gth_clock_scheme.JPG
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Registered: ‎07-30-2007

If the refclk is based on the same oscillator that is driving the input signal, RX,  then it is possible to use either the RXOUTCLK or TXOUTCLK to drive the system.  This would be a synchronous system.  If this is the case it is more normal to use the TXOUTCLK since it is more stable.  If it is not rooted to the same oscillator you may need to separate and use the TXOUTCLK to drive the TXUSRCLKs and the RXOUTCLK to drive the RXUSRCLKs. 

 

To do what you have illustrated in an asynchronous system you could make it synchronous by driving the recovered clock off chip with the OBUFDS_GTE*, sending it through a PLL chip to clean it an bring it to reference clock quality, and then using it to drive the refclk input.

 

BUFG_GTs are global buffers and can drive anything a regular BUFG can drive.  They are just located near the GT and are intended to buffer GT clocks like you are doing here.

 

 




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Registered: ‎02-18-2015

gulotta wrote:
....
I'm trying to figure out if the BUFG_GT can really drive user logic directly as implied by some figures in UG576.  If not then I guess I need a variation to this scheme.  Can someone offer some advice please?..
...

https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf

In page 33 of the above pdf, referring to the BUFG_GT buffers it mentions:

"These clock buffers are located in the HCS and are directly driven by the GT output clocks. Their purpose is to directly drive hard blocks and logic in the CRs via routing and distribution resources."


Kind regards,
Nassos

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Registered: ‎06-05-2010

Thanks.  I saw that.

 

I'm looking for recommendations on a workable clock scheme for the application I described and illustrated.  It would be great if someone from the Xilinx app team can respond and/or contact me at mgulotta@fpgaace.com.

 

Thanks,

Mike

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Registered: ‎07-30-2007

If the refclk is based on the same oscillator that is driving the input signal, RX,  then it is possible to use either the RXOUTCLK or TXOUTCLK to drive the system.  This would be a synchronous system.  If this is the case it is more normal to use the TXOUTCLK since it is more stable.  If it is not rooted to the same oscillator you may need to separate and use the TXOUTCLK to drive the TXUSRCLKs and the RXOUTCLK to drive the RXUSRCLKs. 

 

To do what you have illustrated in an asynchronous system you could make it synchronous by driving the recovered clock off chip with the OBUFDS_GTE*, sending it through a PLL chip to clean it an bring it to reference clock quality, and then using it to drive the refclk input.

 

BUFG_GTs are global buffers and can drive anything a regular BUFG can drive.  They are just located near the GT and are intended to buffer GT clocks like you are doing here.

 

 




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Contributor
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Registered: ‎06-05-2010
Thanks Roy!! Great answer especially on the BUFG_GTs.
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Registered: ‎04-18-2017

Hello everyone!

I would like to ask for a little guidance:

 

Is it possible to configure one of the two dedicated GTH reference clock pin pairs of a Quad as an input while the other pair is configured as an output for outputting the Recovered clock (RXRECCLKOUT) of the transceiver?

 

Thanks for your help!

Peter

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