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Observer
Observer
1,074 Views
Registered: ‎10-31-2018

Unable to create slower clock with MMCM or PLL

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My design runs mostly on 32/64MHz, but I have to forward  a serial clock to another device that runs at 4MHz. I am running into problems generating this clock from an MCMM or a PLL. 

With the formula for Fvco being Fvco= Fclkin x M/D and the formula for each of the clockouts being Fout = Fclkin x M/(D x O), my problem is as follows. My clkin will be 32MHz  Fvco needs to be between 600 and 1440MHz, so lets say I set M to 20 to get a Fvco of 640Mhz. D can be left at 1, but to get a clockout of 4MHz, O needs to be 160 which is higher than the maximum of 128. 

I have seen other posts describing a method of using a counter and a bufgce to create a slow clock, but that is for clocks in the kHz. 4MHz seems like a reasonable clock speed, what method would be simplest to create this? Is there a clocking feature that I have missed? 

Thanks so much in advance.

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Moderator
Moderator
1,059 Views
Registered: ‎09-18-2014

Dalepelletron,

 

Couple options I'll list here but the first one is what I think you are looking for:

  1. Use CLKOUT4_CASCADE feature of the MMCM. This should let you get down all the way to 0.036MHz. Attached image below of the option from Clocking Wizard.
  2. You could aslo do what you've found out which is to use a BUFGCE and toggle the CE input every 2 clock cycles with a very small counter.
  3. Or you can see if you can run your other device design at a slightly higher clock frequency so it's above 4.69MHz.

clkout4cascade.JPG

 

Regards,

T

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Moderator
Moderator
1,060 Views
Registered: ‎09-18-2014

Dalepelletron,

 

Couple options I'll list here but the first one is what I think you are looking for:

  1. Use CLKOUT4_CASCADE feature of the MMCM. This should let you get down all the way to 0.036MHz. Attached image below of the option from Clocking Wizard.
  2. You could aslo do what you've found out which is to use a BUFGCE and toggle the CE input every 2 clock cycles with a very small counter.
  3. Or you can see if you can run your other device design at a slightly higher clock frequency so it's above 4.69MHz.

clkout4cascade.JPG

 

Regards,

T

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Visitor
Visitor
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Registered: ‎05-23-2019

Would checking that allow me to divide my single clock as much I would like (down to 0.036MHz)? Or do I need to have multiple clocks fed in?

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