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Registered: ‎02-09-2010

Unable to read temperature from XADC except via JTAG

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I have a custom board with a XC7K160T.

When using the hardware manager via JTAG, I get the chip temperature in real time, even if the FPGA is not programmed, which is fine.
Using either the registers via AXI4Lite, or the temp_out vector in PL, I get always 0.

DXP_0, DXN_0, VREFP_0, VREFN_0, VP_0, VN_0 are all tied to ground.

DCLK is the clock input when using DRP interface. I use AXI4Lite interface, and s_axi_aclk is mentioned nowhere in UG480. So I entered the s_axi_aclk frequency in DCLK Frequency Field. I have added XADC in the bloc design, is it better to use it outside?

XADC_06_30_rogner.png

The busy_out alternates between 0 and 1, which is fine I presume. I did not check his frequency.

When reading register 01h (V_CCINT) I get sometimes 0xA0, sometimes 0x20. Other registers (00h, 02h, 03h, 04h) read always zero.

Edit: the ot_out (Over Temperature Alarm) behaves as expected (I set Trigger at 75.5 and Reset at 70 °C).

Edit: references are XADC Wizard 3.3, Vivado v2019.1, UG480 v1.10.1 (July 23, 2018.)

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Registered: ‎02-09-2010

I have removed the XADC from the bloc design, and changed to DRP Interface, and now it works, in the sense that I can read the temperature in register 0. However using DRP interface, it is not possible to get the temp_out (Temp Bus) in hardware.

I would like to know what was wrong in the Block Design.

By the way, Figure 5-3 "DRP Detailed Timing" on page 75 of UG480 is somehow misleading. As far as I understand, EOC/EOS, ALM[2:0]/OT, BUSY and CHANNEL are largely unrelated to the present DRP read or write operation. I would suggest to not depict them here, because they are depicted in detail in Figures 5-1 and 5-2.

A read operation consists of DEN going high for one clock cycle, while DWE is low. So only a write operation is presented here. Why is it that DO[15:0] changes? What is the point in changing DADDR[6:0] at clock cycle 4? Would be nice to show a write operation followed by a read operation.

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244 Views
Registered: ‎02-09-2010

I have removed the XADC from the bloc design, and changed to DRP Interface, and now it works, in the sense that I can read the temperature in register 0. However using DRP interface, it is not possible to get the temp_out (Temp Bus) in hardware.

I would like to know what was wrong in the Block Design.

By the way, Figure 5-3 "DRP Detailed Timing" on page 75 of UG480 is somehow misleading. As far as I understand, EOC/EOS, ALM[2:0]/OT, BUSY and CHANNEL are largely unrelated to the present DRP read or write operation. I would suggest to not depict them here, because they are depicted in detail in Figures 5-1 and 5-2.

A read operation consists of DEN going high for one clock cycle, while DWE is low. So only a write operation is presented here. Why is it that DO[15:0] changes? What is the point in changing DADDR[6:0] at clock cycle 4? Would be nice to show a write operation followed by a read operation.

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tenzinc
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Registered: ‎09-18-2014

Did you apply a software reset to the IP? Also not sure what else you would expect on some of those registers besides 0 if you have them grounded... For example 03h/04h correspond to our grounded VP/N and VREFP/N...

 

Regards,

T



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Registered: ‎02-09-2010

I am sorry, but I will not go back to a previous version of my design with XADC in the bloc design, because my current version works. I would suggest you to add an ID register in the XADC in order to test the AXI bus. And to clarify the documentation with respect to AXI bus (s_axi_aclk is mentioned nowhere in UG480). Later I had another issue: I want to use averaging and I use only temperature measurement. I had to select "Channel Sequencer" (even if "Single Channel" was more natural) with a very single "Channel Enabled", in order to select "Average Enable". Thank you @goychman  and https://forums.xilinx.com/t5/Other-FPGA-Architecture/XADC-module/m-p/734297 for the idea of using "channel sequencer" (to solve a slightly different issue).

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