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iisbaer
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Registered: ‎08-27-2013

Unclear XPM_CDC_PULSE description

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I wanted to use the XPM_CDC_PULSE to transmit a single pulse from a slower to a slightly faster domain. The description in the Vivado language templates says that a rising edge initiates a pulse transmission in the destination clock domain. The 7 Series Libraries Guide UG953 talks about a pulse of any size which is the same. But theres the sentence "For proper operation, the input data must be sampled two or more times by the destination clock." This appears on every XPM_CDC macro. Does this mean that the pulse must be in minimum two faster clock cycles long? This wouldn't make sense

 

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jmcclusk
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Registered: ‎02-24-2014

No, the two sample requirement is on the receiving synchronizer, which has at least 2 registers in series to sample the pulse from the sending clock domain.     It's pretty simple..   put in a pulse on the sending clock domain, and get a pulse out on the receiving clock domain.   There is a limit to how often you can send a pulse, which is governed by the speed of the receiving clock domain.  In your case, I think it would be safe to send a pulse every 2 clock cycles, since the receiving clock is faster.

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jmcclusk
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Registered: ‎02-24-2014

No, the two sample requirement is on the receiving synchronizer, which has at least 2 registers in series to sample the pulse from the sending clock domain.     It's pretty simple..   put in a pulse on the sending clock domain, and get a pulse out on the receiving clock domain.   There is a limit to how often you can send a pulse, which is governed by the speed of the receiving clock domain.  In your case, I think it would be safe to send a pulse every 2 clock cycles, since the receiving clock is faster.

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iisbaer
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Registered: ‎08-27-2013

Thank's for clarify. I was not sure if the sentence is a description of the IP or a requirement for the usage of the macro.

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Registered: ‎01-20-2016

This still doesn't make sense to me. The Xilinx documentation for XPM_CDC_PULSE states "For proper operation, the input data must be sampled two or more times by the destination clock." The timing diagram in the Xilinx documentation shows a destination clock that samples the input pulse at least two times. A person could conclude from this that the macro does not support the transfer of a pulse from a faster clock domain to a slower clock domain. Furthermore, one could conclude that a pulse can only be transferred from a slower domain to a faster domain if the input pulse is sampled twice by the faster domain. This would significantly limit the usefulness of this macro.

I use this module to transfer a pulse from a faster domain to a slower domain, and it works in functional simulation. I have SIM_ASSERT_CHK set to 1, and I see no assertions in the simulation.

Can Xilinx please clarify the documentation for XPM_CDC_PULSE?

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