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Observer aidenm
Observer
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Registered: ‎11-24-2018

Understanding IO options for recovering serialized data from ADC

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Hello,

I'm an FPGA neophyte, and could use some guidance if anyone has the time.  My task at hand is a very simple one: To grab some data from an ADC. The data sheet makes perfect sense to me, as do the timing relationships stated by the manufacturer, but I'm having trouble figuring how to actually implement the interface to a Zynq 7020.

Here's a visual of the ADC timing showing only one of the eight data lanes.


PhaseDDR.png

At the sampling rate I want to use (60 MHz) and the bit depth (10 bits), this chip drives a 300 MHz DDR bit clock, which seems to be well within the performance allowable for the Zynq 7000 series.

Unfortunately the setup and hold times are given as only 0.6ns typical at the target clock rate, which seems to preclude using statically routed I/O. Indeed, when I synthesize a first guess with the 'datasheet' option checked in, I'm told that setup time for bank 35 (High Range) is ~0.2ns, but hold to clock is a massive 1.8ns.

Reading some more I have guessed that this means that 'static alignment' of clock and data at these speeds is not feasible and instead I will have to rely on an 'ISERDESE2' implementation with bit slipping configured to allow me to dynamically tune the clock to data alignment.

I would love to know if I have understood the situation properly so far, and would also really appreciate guidance on a few open questions I have:

1) Is Bank 35 of a zynq 7020 suitable for this purpose?

2) When using the ISERDES, is it necessary that the clock arrive on a MRCC or SRCC?

3) Given that I have a frame marker present (ADCLK in the above image) is 'autocalibration' of the interface possible, or do I need to provide a fixed pattern on all bit lanes.

 

Thanks in advance, and I am sorry for asking what is probably a simple question. I'm just getting bogged down in the details badly and could use some insight.

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Community Manager
Community Manager
200 Views
Registered: ‎08-08-2007

Re: Understanding IO options for recovering serialized data from ADC

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Hi @aidenm 

 

There is a 7 Series Xapp for ADC interfacing that may be of use to you  Xapp 524.

 

1) Is Bank 35 of a zynq 7020 suitable for this purpose?

Not sure what package you are using but as long as its a High Range (HR) (there are no HP on the 7020) 

2) When using the ISERDES, is it necessary that the clock arrive on a MRCC or SRCC?

Yes

3) Given that I have a frame marker present (ADCLK in the above image) is 'autocalibration' of the interface possible, or do I need to provide a fixed pattern on all bit lanes.

The Xapp mentioned above uses the FCLK as the frame marker, it captures & deserializes to to find where the frame is placed and uses that to bitslip the data lanes. 

 

Sandy

 

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Community Manager
Community Manager
201 Views
Registered: ‎08-08-2007

Re: Understanding IO options for recovering serialized data from ADC

Jump to solution

Hi @aidenm 

 

There is a 7 Series Xapp for ADC interfacing that may be of use to you  Xapp 524.

 

1) Is Bank 35 of a zynq 7020 suitable for this purpose?

Not sure what package you are using but as long as its a High Range (HR) (there are no HP on the 7020) 

2) When using the ISERDES, is it necessary that the clock arrive on a MRCC or SRCC?

Yes

3) Given that I have a frame marker present (ADCLK in the above image) is 'autocalibration' of the interface possible, or do I need to provide a fixed pattern on all bit lanes.

The Xapp mentioned above uses the FCLK as the frame marker, it captures & deserializes to to find where the frame is placed and uses that to bitslip the data lanes. 

 

Sandy

 

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Observer aidenm
Observer
195 Views
Registered: ‎11-24-2018

Re: Understanding IO options for recovering serialized data from ADC

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Thanks @sandrao ,

 

To quickly clarify (ordering boards today if possible) does the FCLK have to also come in on a SRCC or is it treated as just another data lane?

 

Thanks again.

After reading the XAPP it looks like FCLK is treated like just another data lane. Thanks again.

 

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