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a.gamez
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Registered: ‎05-12-2016

Unsupported clocking topology used for ISERDESE2 when driving clock from MMCM

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Hi

 

I'm getting this DRC error when routing an ISERDESE2 using NETWORKING interface type.

Unsupported clocking topology used for ISERDESE2 system_i/art_adc3442_0/U0/gen_1wire_adc[0].u_art_adc344x_1wire/DeserializerMaster. This can result in corrupted data. The system_i/art_adc3442_0/U0/gen_1wire_adc[0].u_art_adc344x_1wire/DeserializerMaster/CLK / system_i/art_adc3442_0/U0/gen_1wire_adc[0].u_art_adc344x_1wire/DeserializerMaster/CLKDIV pins should be driven by the same source through the same buffer type or by a BUFIO / BUFR combination in order to have a proper phase relationship. Please refer to the Select I/O User Guide for supported clocking topologies of the chosen INTERFACE_TYPE mode.

I don't understand the reason for this, because CLK and CLKDIV are generated by an MMCM which is routed:

 

Screenshot_2020-01-30_08-34-26.png

 

 

CLK_IN1 [175MHz Differential clock capable pin] ->
                bit_clk -> 175MHz BUFG
                frame_clk -> 25MHz BUFG
                frame_clk2x -> 50MHz BUFG

Both bit_clk and frame_clk are the clocks I pass to ISERDESE2. The last clock is used later on for signal processing, but the thing is that I believe I am meeting the requirement of CLK and CLKDIV being driven by the same source. From UG471:

CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or
PLL
When using a MMCM to drive the CLK and CLKDIV of the ISERDESE2, the buffer types
suppling the ISERDESE2 can not be mixed. For example, if CLK is driven by a BUFG, then
CLKDIV must be driven by a BUFG as well. Alternatively, the MMCM can drive the
ISERDESE2 though a BUFIO and BUFR.

So, what is wrong with this?

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sandrao
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Registered: ‎08-08-2007

Hi @a.gamez 

 

You can place a IDELAY on the input clock path for a 7 Series design. You cannot place the IDELAY on the output of the MMCM.

 

The IDELAY has a granularity of 78ps or 52ps. The MMCM fine phase shift is 1/56*Fvco, if you've a Fvco of 1G that give a granularity of ~18ps, which is more granular.

 

Thanks,
Sandy

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sandrao
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Registered: ‎08-08-2007

Hi @a.gamez 

You should be able to have two clocks from a MMCM drive the CLK and CLKDIV of an ISERDES in 7 Series. I've done it and nore seen DRC.

What version of Vivado are you using?

Would you be able to share HDL (including the ISERDES and Clk Wiz) that I can implement in Vivado to reproduce the issue?

 

 

Thanks,
Sandy

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a.gamez
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Hi @sandrao 

Vivado version is 2018.2

I'm not allowed to share publicly this code, but I think should be able to generate a proof of concept removing the other elements in my design that I can share, but I'll have to ask my superiors about that, I'll try as hard as possible, it's probably a good idea regardless if I can share it or not.

Thanks!

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sandrao
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Registered: ‎08-08-2007

Hi @a.gamez 

 

The simplier the testcase the better. If you can strip is back to the barebones of the ISERES and Clocking Wizard and nothing else and can still the issue that would be what we'd need.

 

 

Thanks,
Sandy

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a.gamez
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Registered: ‎05-12-2016

Hi,

I must add some information that I believe is the clue on this that I've just realized when trying to build a smaller design to demonstrate the issue.

I mistakenly explained that CLK and CLKDIV ports were connected straight out of the Clocking Wizard to the ISERDESE module. This is not true. Both clocks are passed through an IDELAYE2 primitive.

If the clocks are not passed through the IDELAYE2 primitive I found it's impossible for the ISERDESE to sample in the center of the bit, so I added those modules. But no buffer is added after the IDELAYE2 primitive. Should I add one after the IDELAYE2?

Thanks

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a.gamez
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Also, which is the right way to generate negated CLK, CLKB? A not gate? And shall it pass through another BUFIO?

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a.gamez
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Registered: ‎05-12-2016

Hi

I solved the warnings by manually placing a pair of BUFIO/BUFR entities.

But the problem now is that ISERDESE loses track of the optimum sampling point of bit/word.

I have designed a way to calibrate ISERDESE using also an IDELAYE2 for data that, using a pattern at the input, is able to find a value for BITSLIP and IDELAY, and I can see my data to be perfectly equal as the stream of bits I feed into the input. After quite a time (~60 seconds) the data desynchronizes completely and there's some shift in bits and words.

This was working better before, even with the DRC warnings. I don't really understand much of what is going on...

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sandrao
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Registered: ‎08-08-2007

Hi @a.gamez 

 

You are correct that the problem would be coming out from an MMCM and going to IDELAYs that is not a supported clocking topology.

As you need to delay you clock I would suggest that you look at the phase shift options of the MMCM, take a look at the Phase Shift section of the clocking UG : https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Thanks,
Sandy

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a.gamez
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Hi @sandrao 

I will try, but I'm not sure it's going to do what I need.

Right now I was delaying bit clock by only a couple of taps of the IDELAYE2 (0-156ps), while using MMCM the least I am able to modify my clock phase is 5.625, which is quite a lot compared to the few picoseconds that seem to be needed to fix my time differences.

Isn't there anything with more granularity, like IDELAYE2?

Thanks!

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a.gamez
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Hi again @sandrao 

I don't understand why I can't add an IDEALYE2 to the clock path, given that SelectIO allows exactly that. How can I do this in VHDL?

Thanks!

 

Screenshot_2020-02-04_13-05-01.png

 

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sandrao
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Registered: ‎08-08-2007

Hi @a.gamez 

 

You can place a IDELAY on the input clock path for a 7 Series design. You cannot place the IDELAY on the output of the MMCM.

 

The IDELAY has a granularity of 78ps or 52ps. The MMCM fine phase shift is 1/56*Fvco, if you've a Fvco of 1G that give a granularity of ~18ps, which is more granular.

 

Thanks,
Sandy

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a.gamez
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Registered: ‎05-12-2016

Thanks @sandrao !

I've solved it by placing the IDELAY just at the input of the clock path as you recommended, before attacking the MMCM. It does synthesize and seem to produce the best results I've got until now.

Thanks a lot!

 

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