UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer rammi
Observer
846 Views
Registered: ‎04-13-2018

Unused pins of DDR3L SDRAM controller bank

Jump to solution

Hii

 

In our current design, we are  using Artix-7(XC7A75T-1FGG676I). 

In that we have 8Gb ddr3l and it occupies two banks of FPGA. So unused IOs in that bank 

 

 

Can i use the unused IOs  in DDR3L SDRAM controller bank as a GPIO ?

Any limitations are there to use unused pins as GPIO ??

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
942 Views
Registered: ‎11-28-2016

Re: Unused pins of DDR3L SDRAM controller bank

Jump to solution

Hello @rammi,

 

You will be limited to the voltage range supported in that I/O bank, and with DDR3 that's either 1.5V or 1.35V.

0 Kudos
3 Replies
Moderator
Moderator
813 Views
Registered: ‎11-28-2016

Re: Unused pins of DDR3L SDRAM controller bank

Jump to solution

Hello @rammi,

 

When you have unused pins that are in the same byte as a memory interface then you can use them as GPIOs.


When you have an unused byte that's in the same bank of a memory interface then you can use it as anything like GPIOs or a PMOD interface.

 

 

0 Kudos
Highlighted
Observer rammi
Observer
787 Views
Registered: ‎04-13-2018

Re: Unused pins of DDR3L SDRAM controller bank

Jump to solution

Thanks @ryana

 

Shall i use these unused pins as a LVTTL(3.3V) IO lines???

 

 

0 Kudos
Moderator
Moderator
943 Views
Registered: ‎11-28-2016

Re: Unused pins of DDR3L SDRAM controller bank

Jump to solution

Hello @rammi,

 

You will be limited to the voltage range supported in that I/O bank, and with DDR3 that's either 1.5V or 1.35V.

0 Kudos