06-02-2016 07:05 PM
I have a question regarding the Xilinx XC7A35T-L1CSG324I (Artix 7) VCCO voltages .
I will be running using Master SPI x4 configuration.
Bank 0 will be 1.8V, Bank 14 and 15 will be 1.5V.
SPI flash IC will be powered at 1.8V and connected to Bank 14 (there are no 1.5V SPI Flash). DDR3 IC will be powered at 1.5V and connected to bank 14 and 15.
CFGBVS will be low.
According to configuration guide UG470, V1.10, page 13 paragraph 2:
" When CFGBVS is tied to GND for 1.8V/1.5V I/O operation, then if any configuration I/O are used in bank 14 or bank 15, VCCO_14 or VCCO_15 and the configuration I/O signals to bank 14 or bank 15 must be 1.8V or 1.5V to avoid device damage."
Does that mean I can use 1.8V SPI Flash since I meet "... must be 1.8V or 1.5V to avoid damage." Or else can I add 100 ohm series termination resistors to SPI signals to drop the input voltage to FPGA ?
06-02-2016 09:54 PM
You can use 1.8V, but if there is memory interface in the same bank please check the voltage levels from the datasheets, a level translator may be needed
Below discussions can help
06-02-2016 10:40 PM
06-02-2016 11:24 PM
Sorry I forgot to mention that SPI Flash at bank 14 is for Master SPI configuration. It is a 1.8V device, there are no 1.5V SPI flash on the market I know of that can be used as configuration ROM. I intend to power the IC at 1.8V.
Also, Bank 14 VCCO is connected to 1.5V. Bank 14 is connect to a 1.5V DDR3.
I do not intend to use a voltage translator between FPGA and SPI Flash because the FPGA does not output a direction control signal for level translator.
So I would like to know if the FPGA can accept 1.8V input during configuration when its VCCO is 1.5V. After configuration, the SPI Flash is still driving 1.8V input FPGA. If not, any mitigating circuits? Note CFGBVS is connected to gnd.