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Visitor
Visitor
11,610 Views
Registered: ‎12-07-2012

Using GTGREFCLK with GTX transceivers for testing purposes

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Hi there, the QPLL and the CPLL of the GTX transceivers in Kintex7 can both be clocked from the GTGREFCLK, for internal testing purposes. I would like to do some testing on an eval board and it would greatly simplify my design if I could use a clock signal that does not come from an IBUFDS. Is it -- for example -- possible to use a MMCM output and connect it to the GTGREFCLK to drive the QPLLs/CPLLs? Thanks in advance for any help! Best, Czawbar
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Community Manager
Community Manager
14,468 Views
Registered: ‎07-23-2012
Hi Czawbar,

The GTREFCLK can be provided from a fabric clock (Eg clock output of a MMCM).

But this is highly not recommended. Because using the fabric clock adds lot of skew to the GTREFCLK.

If you still want to use it, then you need to connect the input of QPLL/CPLL to the output of an MMCM and change the QPLLREFCLKSEL/CPLLREFCLKSEL to an appropriate value (which can be found in UG476).

Regards,
Krishna
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Community Manager
Community Manager
14,469 Views
Registered: ‎07-23-2012
Hi Czawbar,

The GTREFCLK can be provided from a fabric clock (Eg clock output of a MMCM).

But this is highly not recommended. Because using the fabric clock adds lot of skew to the GTREFCLK.

If you still want to use it, then you need to connect the input of QPLL/CPLL to the output of an MMCM and change the QPLLREFCLKSEL/CPLLREFCLKSEL to an appropriate value (which can be found in UG476).

Regards,
Krishna
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Community Manager
Community Manager
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Registered: ‎07-23-2012
The CPLLREFCLKSEL/QPLLREFCLKSEL setting to choose GTGREFCLK (fabric clock) as CPLL/QPLL input is 3'b111.

Regards,
Krishna
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Moderator
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11,590 Views
Registered: ‎02-16-2010
Please refer to AR#53500
http://www.xilinx.com/support/answers/53500.html
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Visitor
Visitor
11,578 Views
Registered: ‎12-07-2012

Thanks a lot for your help!

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10,406 Views
Registered: ‎03-20-2014

Hi,

 

I'm currently working on GTX with Zynq ZC706, when i instantiate MMCM in IBERT example design and connect output of MMCM to the GTGREFCLK to drive the QPLLs/CPLLs (CPLLREFCLKSEL/QPLLREFCLKSEL is set to b111) generating bitstream Drc issues an error:

 

[Drc 23-20] Rule violation (REQP-52) connects_GTGREFCLK_ACTIVE - GTXE2_CHANNEL cell u_ibert_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gtxe2_channel: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.

 

Any advice would be appreciated. Thank you!

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Xilinx Employee
Xilinx Employee
10,402 Views
Registered: ‎01-03-2008

The REFCLK clock for the GT block must be driven from an external low jitter clock source.  Using an internally generated clock would add a significant amount of jitter to the link.

 

The ZC706 has multiple options for the reference clock source.

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Visitor
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Registered: ‎03-18-2020

Hello,

I know this is a very old question, but I came across it while modifying an old design. In this design this same problem appears with a Gen2 PCIe core. Now, PCIe embeds it's clock withing the data itself (like any fast serial transceiver). I don't understand why it is so important to feed the clock to the transceiver core correctly then... I mean, this is not a system-synchronous case, where both TX/RX receive the clock externally and use it to drive and read the data line...

Coul somebody explain?

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