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Observer lasthorizon711
Observer
1,185 Views
Registered: ‎07-31-2018

Using SERDES with differential input signals

Hi there, 

 

I have an device that provides LVDS data into a Spartan-7 FPGA and am looking for some clarification about correct design technique for the ISERDESE2 used to capture the data. 

 

Should I have an ISERDESE2 for each of the positive and negative half of the differential pair or use the BUFDS to turn the differential signal into a single-ended signal and use just one ISERDESE2?

 

Having two SERDES does allow comparison between the two halfs of the input signal to error check, but I feel this maybe redundant?

 

Cheers

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14 Replies
Xilinx Employee
Xilinx Employee
1,131 Views
Registered: ‎06-30-2010

Re: Using SERDES with differential input signals

normally most customers would use an IBUFDS and then have a single SERDES. However it depends on what type of alignment you are doing, is the clock being sent, if the clock data alignment known?
Are you planning on doing real time window monitoring. if you are doing something complex like that then an IBUFDS_DIFF_OUT can be used and the P and N sides sampled and compared. that is what we have in some XAPPs but if you are not planning anything like that i would stick to a single SERDES
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Observer lasthorizon711
Observer
1,117 Views
Registered: ‎07-31-2018

Re: Using SERDES with differential input signals

I am using it to sample high speed ADC data with the ADC providing the clock and frame signal. 

 

Ideally I would like to not have to include additional logic for sampling and aligning on-the-fly if it isn't necessary. 

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Moderator
Moderator
1,107 Views
Registered: ‎04-18-2011

Re: Using SERDES with differential input signals

Without knowing the data rate you are using or the ADC and how the clock and data are aligned its hard to suggest to you what you should do.
Take a look at this xapp for some guidance
https://www.google.ie/url?sa=t&source=web&rct=j&url=https://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf&ved=2ahUKEwjvq8Omu47eAhXHJcAKHZrqBJ0QFjAAegQIBhAB&usg=AOvVaw1RxCiSO5I55IEmxWG_hPNA
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Adventurer
Adventurer
1,099 Views
Registered: ‎03-30-2011

Re: Using SERDES with differential input signals


@lasthorizon711 wrote:

I am using it to sample high speed ADC data with the ADC providing the clock and frame signal. 

 

Ideally I would like to not have to include additional logic for sampling and aligning on-the-fly if it isn't necessary. 


This depends on you sampling clock. What's the sample rate you are targeting?

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Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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Observer lasthorizon711
Observer
1,073 Views
Registered: ‎07-31-2018

Re: Using SERDES with differential input signals

Sampling rate of (initially) 1.125GHz DDR 

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Adventurer
Adventurer
1,063 Views
Registered: ‎03-30-2011

Re: Using SERDES with differential input signals

At this rates, I definitly would suggest to use the IBUFDS_DIFF_OUT buffers and create some logic for doing realtime window monitoring.

 

If this is no option, I would at least instantiate some IODELAYs with fixed delay settings on the data lines (if delay compensation is necessary due unmatched lane length) and a programmable delay on the clock line. Then you can tap through the delay values and determine what the min and max delay values are when transmission errors starts to occur. The average between min and max is probably the best sampling point of your windows.

 

Keep in mind to keep the temperature constant when using fixed delay settings.

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Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
Moderator
Moderator
1,047 Views
Registered: ‎04-18-2011

Re: Using SERDES with differential input signals

@ttobsen

You won't close timing on this interface at this data rate statically. 

You will need to dynamically capture the input. 

As important as the data rate, you must also be conscious of the clock and data allignment at the ADC. 

 

Go with something like XAPP524. 

This xapp does real time monitoring but also at the start it is able to re-postition a centre alligned clock in the data eye. 

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Observer lasthorizon711
Observer
1,043 Views
Registered: ‎07-31-2018

Re: Using SERDES with differential input signals

What if the data rate was reduced to 625MHz DDR? Would the SERDES arrangement be able to cope without dynamic window alignment?

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Adventurer
Adventurer
1,021 Views
Registered: ‎03-30-2011

Re: Using SERDES with differential input signals

@klumsde

 

There is no hard limit where you can say: with this rate, do realtime monitoring and adjustment and below you haven't. It depends on how constant can you keep your environment parameters like temperature or supply voltage.

 

But why I ask is, that you have a minimum rate where implementing realtime monitoring is done pretty easily. Your IODelays can adjust the line delay about 78 ps (when using 200 MHz reference clock) per tap. This leads to a maximum of 31x78 ps = 2418 ps window size your data bits should have, to completly monitor one bit from one edge to the other.

 

As I guess I suggest to use bit-alignment techniques when one UI of your data bit is smaller than 2400 ps, which in your case is fullfilled (even with 625 MHz DDR). But it is just a suggestion of me and no Xilinx recommendation. In the end, you need to measure if you need realtime window monitoring. The good thing: FPGAs are easily reprogrammable, so you can anytime implement realtime bitalignment if you see that your captured data gets messed up when running for a while.

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Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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Adventurer
Adventurer
979 Views
Registered: ‎03-30-2011

Re: Using SERDES with differential input signals

Are you sure that this really is the case? I don't think you can say that definitely realtime monitoring techniques must be implemented, but the likelihood that this is needed is very high at this rates.

Theoretically, if it is possible to create reproducible a system with low jitter and a minimum of TIE and can be possible to use a statical timing. But I doubt that this is will be achieved in practice (even if, the effort for this system is much higher than implementing a realtime bitalignment).

 

@klumsde

Are you sure that this really is the case? I don't think you can say definitely that realtime monitoring techniques must be implemented, but the likelihood that this is needed is very high at this rates.

Theoretically, if it is possible to create reproducible a system with low jitter and a minimum of TIE and can be possible to use a statical timing. But I doubt that this is will be achieved in practice (even if, the effort for this system is much higher than implementing a realtime bitalignment).

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Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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Observer lasthorizon711
Observer
957 Views
Registered: ‎07-31-2018

Re: Using SERDES with differential input signals

Since we are talking about frequencies and data rates at the moment, I am just running the design through implementation and timing analysis. This is reporting a Min Period fail with a slack of -0.670

 

The device I am using is a Spartan-7 XC7S50 speed grade - 2

 

I have followed the design documentation for clocking schemes for the SERDES which use a BUFIO to provide the high speed serial clock and a BUFR to provide the low speed CLKDIV. 

 

From the AC/DC switching characteristics I have found the Fmax of the BUFR device to be 375MHz. 

 

With an input clock of 1.25GHz, this causes the timing fail. Using an input clock of 625MHz passes the timing analysis (pulse width), however, in my mind this does not stack up. (625MHz > 375MHz). Can someone please explain?

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Adventurer
Adventurer
949 Views
Registered: ‎03-30-2011

Re: Using SERDES with differential input signals

As you can see in DS189, the Spartan 7 (with Speedgrade -2) is limited to 1250 Mb/s when using DDR and LVDS. Therefore your maximum allowed clock are 625 MHz.

 

But the 625 MHz clock should not feed a BUFR (which you are right is limited to 375 MHz), you have to feed a BUFIO which can be driven by max 680 MHz. When using ISERDES you should use the BUFR for creating the lowspeed clock for the parallel data and feed the highspeed clock input with a BUFIO.

 

I recommend to go through UG471, especially the section 3 with the ISERDES stuff. There are some clocking topologies explained.

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Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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Observer lasthorizon711
Observer
942 Views
Registered: ‎07-31-2018

Re: Using SERDES with differential input signals

In UG471, figure 3-6 shows a BUFIO/BUFR clocking scheme for the SERDES (which is what has been followed).

 

I am thinking though, that the source for the BUFR may have to come from an internal MMCM/PLL. The documentation (UG471) says I can provide the clock source from either the real world OR an MMCM. Obviously phase alignment is key, therefore mixing these would not be a good idea. To me, this results in a need to generate both the 625MHz clock and the 156MHz from a PLL and using a delay line to align the generated clock signal with the eyes of the incoming data - naturally more complicated than using the clock source from the ADC. 

 

Am I right in my thinking?

 

 

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Adventurer
Adventurer
918 Views
Registered: ‎03-30-2011

Re: Using SERDES with differential input signals

You're right, you can use a MMCM/PLL to feed the low speed clock for the parallel data. The phase alignment needs to handle to capture the incoming highspeed data, which needs to be done in your case using the IODELAY buffers.

So it doesn't matter if you are using a MMCM or an BUFR for driving the lowspeed clock.
------------------------------------------------------------
Ingenieurbüro Tobias Baumann / FPGA & Embedded System Solutions / https://www.elpra.de
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