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ronnu
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Registered: ‎10-14-2017

Using both LVDS and LVCMOS18 in one bank

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I would like to know if it is possible to use both the LVDS and LVCMOS IOSTANDARDS in one and the same I/O bank. I mean if for example with z7030 device I power the bank 35 with 1.8V, then can I assign IOSTANDRAD for some pins in this bank to be LVDS (and enable internal termination) while assigning LVCMOS18 for some other pins in this bank? Or is this kind of mixing un-allowed and I should place pins requiring LVCMOS18 into some other banks (13 for example).

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ddn
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Registered: ‎06-06-2018

Hi @ronnu ,

Sorry, just want to recap to make sure I get this correct. So if I have some pins configured as inputs and using both LVDS and LVCMOS18 on those pins then this would not be allowed?

>>> Yes, if you declare LVCMOS18 and LVDS as Inputs, then you can combine them in a same bank, since Both require same VCC voltages and is not violating rule 2.

The same is for pins configured as outputs - if having the same Vcco, but assiging LVDS to some  of the pins and LVCMOS18 to others, then this would not be allowed?

>>> Yes, if you declare LVCMOS18 and LVDS as Outputs, then you can combine them in a same bank, since Both require same VCC voltages and is not violating rule 1.

 

Regards,
Deepak D N
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ddn
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Registered: ‎06-06-2018

Hi @ronnu ,

Please refer page 97 of UG471 (v1.10), which talks about "Rules for Combining I/O Standards in the Same Bank". And also refer Table1-55.

This clarifies your query.

Hope this helps.

Regards,
Deepak D N
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ronnu
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Registered: ‎10-14-2017

Hi @ddn 

I already looked at that paragraph in UG471 and based on that I understand that this hould be allowed, but I'm not sure hence the question. Can you please confirm that this kind of mixing is allowed?

Thank you!

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ddn
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Registered: ‎06-06-2018

Hi @ronnu ,

I hope Bank 35 is a HP Bank.

Since you have not specified LVCMOS18 is Input/output/bidirectional and LVDS as Input/output/bidirectional. I will give you possible answers based on Input/output/bidirectional for IO standards you have choosen.

 

First Case: LVDS with Internal Termination ( Input IO Standard)

                   LVCMOS18 (Input IO Standard).

                  >> Combination  possible, since not violating Rule2.

Second Case : LVDS with Internal Termination ( Input IO Standard)

                         LVCMOS18 (Output IO Standard).

                   >> Combination possible. Since Both IO Standard requires same VCC voltage and is not violating Rule3.

 

Third Case:      LVDS with Internal Termination ( Input IO Standard)

                         LVCMOS18 (Bidirectional IO Standard).

                >> Combination  possible, since not violating Rule4.

Regards,
Deepak D N
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ronnu
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Registered: ‎10-14-2017

Thank you!

I have no bi-directional pins int his bank, only inputs and outputs.

Sorry, just want to recap to make sure I get this correct. So if I have some pins configured as inputs and using both LVDS and LVCMOS18 on those pins then this would not be allowed? I don't really understand how this violates rule 2, can you please elaborate? The Vcco is the same for both IOSTANDARDS.

The same is for pins configured as outputs - if having the same Vcco, but assiging LVDS to some  of the pins and LVCMOS18 to others, then this would not be allowed?

Thank you for your help!

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ddn
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Registered: ‎06-06-2018

Hi @ronnu ,

Sorry, just want to recap to make sure I get this correct. So if I have some pins configured as inputs and using both LVDS and LVCMOS18 on those pins then this would not be allowed?

>>> Yes, if you declare LVCMOS18 and LVDS as Inputs, then you can combine them in a same bank, since Both require same VCC voltages and is not violating rule 2.

The same is for pins configured as outputs - if having the same Vcco, but assiging LVDS to some  of the pins and LVCMOS18 to others, then this would not be allowed?

>>> Yes, if you declare LVCMOS18 and LVDS as Outputs, then you can combine them in a same bank, since Both require same VCC voltages and is not violating rule 1.

 

Regards,
Deepak D N
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