V7 GTH RXCDR_CFG Settings For SSC

[chsdkj]

UG476, 7 Series FPGAs GTX/GTH Transceivers User Guide, v1.11.1, on p.206 and 207 has Table 4-20, GTH CDR Recommended Settings for Scrambled/PRBS Data (No SSC).

Similar information is needed for the case of SSC being used, for datarates of 5Gb/s and 10Gb/s scrambled data with 0-5000ppm downspread SSC, such as is encountered in USB3.1 Gen1 and Gen2 signaling.

[venkata]

I think USB 3.1 is not characterized yet.

You can use the SATA settings for 5Gbps.
http://www.xilinx.com/support/answers/63869.html

[chsdkj]

Thanks, however AR #63869 merely discusses keeping the CDR circuitry in Hold during link initialization, and does not outline any RXCDR_CFG values.  Even UG476 indicates an SSC RXCDR_CFG value only for GTX xcvrs, and not for GTH xcvrs.

Any idea when USB3.1 RX is expected to be characterized on V7 GTH xcvrs?

[venkata]

Check AR#53364
http://www.xilinx.com/support/answers/53364.html

[chsdkj]

Thanks, however that AR outlines different GTH settings for SSC RX for only 1.5Gb/s, 3Gb/s and 6Gb/s datarates.  How would it be determined what the appropriate values would be for 5Gb/s and 10Gb/s datarates?

Additionally, note that for USB3.1 the encoding is not the usual 8b/10b as utilized in SATA, but rather a 128b/132b long-run-block encoding, which would possibly/presumably have some effect on what RX settings would be required, and whether such RX is even possible reliably.

Is GTH 10Gb/s RX w/ SSC for 128b/132b encoding possible/supported on any Xilinx FPGA?

[venkata]

128b/132b encoding is not supported with GT until UltraScale FPGAs also. This needs to be implemented in fabric if required.

[chsdkj]

Handling the actual datastream encoding/decoding is not a particular issue for our requirements.  What is important however is (knowing simply) whether/that the V7 GTH xcvr can succussfully in fact "do the RX" on such a 10Gb/s SSC datastream.

[jimian_tw]

---

@venkata wrote:
Check AR#53364
http://www.xilinx.com/support/answers/53364.html

---

We have the same problem on the RXCDR_CFG settings for USB3 SSC as well.

In our case, we want to use GTH to implement a USB3 PHY that can work together with our existing USB3 PCS and link layer designs, that has been verified using conventional PHY.

I tried your suggestion and applied the recommended settings in AR#53364 before, but our PCS couldn't achieve symbol lock on the resulting Rx data from GTH.

Id like to try adjusting RXCDR_CFG myself, but without knowing how RXCDR_CFG works, it is hard to perform such experiments.

So I'd like to know where I can find assistance on solving such issues.

Thank you!