UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor keeganrm
Visitor
6,393 Views
Registered: ‎01-17-2017

VC707 BPI Flash Access using AXI EMC

Jump to solution

Hi all,

 

I'm using the VC707 (Virtex-7 eval board) and I'm attempting to read/write to the 128MB BPI flash memory on board in asynchronous read mode (also programming the VC707 in asynch mode).

 

In my design, I have an state machine that generates AXI read/write requests for an AXI crossbar switch. The AXI crossbar is switching between the AXI EMC, and the MIG (for the DDR3). 

 

I can successfully read/write to the RAM, but when I attempt to read from the flash memory, I get a response that I don't understand. 

 

The base address for the AXI EMC in the crossbar switch is 0x8000.0000. 

 

When I read from the first flash addresses in memory (0x8000.0000 --> 0x8000.0038), I get a return of all zeros.

When I read from the next memory address (0x8000.003C), my I receive all zeros again, but then I see multiple pulses on the EMC's s_axi_mem_rready output port (instead of just the one pulse to signify the response to my one read request), which makes me think that somehow the EMC is trying to read out more data.

 

I've been trying to read through the AXI EMC / PC28F00AG18FE (flash) documentation, but I can't figure out what's going on. If anyone is successfully communicating to the flash on the VC707 using the AXI EMC core in asynchronous mode, I would appreciate any resources or guidance with this. 

 

 

Below are some more details about the EMC configuration.

 

I am using a generated 100MHz clock for both the AXI and RD clock input ports on the EMC core.

 

My AXI EMC IP core configurations are below:

EMC Board Interface

Custom

AXI Data Width

64 bits

AXI ID Width

                                           0 bits

Number of Memory Banks

                                               1

Base Address

0x0000.0000

High Address

0x0FFF.FFFF

Memory Type

Linear Flash

Data Width

16

Parity

No Parity

Delay Model

Flow Through Model

 

My EMC timing parameters are below:

Read CE Low to Data Valid Period

tELQV

96000

Read Address Valid to Data Valid Period

tAVQV

96000

Page Access Period

tAPA

15000

Read CE High to Data Bus HZ Period

tEHQZ

7000

Read OE High to Data Bus HZ Period

tGHQZ

7000

Write Cycle Period

tCW = ( tWLWH + tELWL + tWHEH )

40000

 
 

Write Enable Min. Pulse Width

tWLWH

40000

Write Phase Period

tWHWL

20000

Write WE High to Data Bus LZ Period

tWHGL

20000

Write Recovery Period For Flash Memory

tBHWH

200000

 

 

Thanks in advanced for any help!

 

Keegan

0 Kudos
1 Solution

Accepted Solutions
Visitor keeganrm
Visitor
8,742 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@pratham Thanks for the response. I now understand why the EMC core ends up tying ADV# to ground, but this limits the functionality of the IP core, as ADV# is used to latch the upper-order bits of the address bus, so that the Asynchronous page read mode can be utilized.

 

That being said, I'm not trying to use the buffered-page read mode, I'm trying to configure the EMC to use single-beat AXI transactions, so I have no use for the ADV# pin. 

 

As I'm trying to set it up for single beat transactions, I statically set the following ports: 

axi_a*burst => "01" , -- increment burst type
axi_a*size => "001" , -- 2 bytes per transfer (because the flash is a 16-bit bus)

 

With those read/write AXI ports set statically, and the AXI read/write length (axi_a*len) set to X"00", the each AXI read/write transaction should be a single-beat with 2 bytes, correct? 

 

I'm still having an issue with the core though, because my AXI write requests to the EMC IP seem to cause the flash address bus to increment four times. When I attempt to write the Read Status Register command to the EMC core at address 0x81020000, I see the address bus first get set to 0x81020000, then 0x81020002, 0x81020004, and 0x81020006, then back to 0x81020000. On each address transition I also see that CEN toggles (so the EMC core is writing the Read Status Register Command to four different addresses each time I want to only write to one).

 

I had the same issue with the incrementing address during AXI read requests, before I configured the AXI ports as I described above. When I updated the AXI ports to statically set them to the values above, the address no longer incremented four times during the read, instead the address bus stayed the same during the entire transaction.

 

I have the same configuration on both arburst/awbust and arsize/awsize, yet I'm now only seeing this issue during the write request, so I'm not really sure where to go from here. 

 

 

 

0 Kudos
13 Replies
Xilinx Employee
Xilinx Employee
6,368 Views
Registered: ‎08-02-2007

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

hi,

 

did you get a chance to look at the axi_emc configuration available in the BIST design?

https://www.xilinx.com/support/documentation/boards_and_kits/vc707/2015_1/xtp205-vc707-bist-c-2015-1.pdf

 

--hs

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Scholar pratham
Scholar
6,358 Views
Registered: ‎06-05-2013

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@keeganrm If above link does not help you proceed further, let us know. I think I might have a working design on VC707 async read.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Visitor keeganrm
Visitor
6,330 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@htsvn So I haven't looked at the 2015 VC707 BIST design, but I have the 2016 VC707 BIST design (which I assume is very similar, yes?). 

 

 

 

I have been trying to use a custom AXI implementation to generate read/write requests (instead of the Microblaze IP core) and as I said, it works when communicating with the MIG to read/write to RAM. Should the AXI EMC IP core communicate the exact same way, or is it different and necessary to use the Microblaze to generate requests to the EMC core? It's hard to understand what 

 

Another thing that I noticed is that the EMC base address is different (not 0x0000.0000) in these designs. In my design, I have a AXI crossbar that routes my AXI requests to both the DDR3 (starting at base address 0x0000.0000), and the EMC core (starting at base address 0x8000.0000). If my crossbar switch is configured this way, do I also have to specify in the EMC IP configuration a base address of 0x8000.0000 (and a high address of 0x8FFF.FFFF)? The AXI switch has an address bus of 32-bits, but the flash on the VC707 only has a 26-bit address bus, so when I had originally configured the switch, I assumed that the higher ordered bits would get ignored by the EMC core. It's easy enough to reconfigure this to reflect the address offset and check whether that fixes the issue, so I'll go ahead and try it.

 

@pratham I think these BIST designs configure the flash for synchronous reads. If you have a working design for the VC707 doing async reads/writes, could you confirm my timing configurations from the Original Post (or possibly send me the design so I can compare)? Also, does this design you have use the Microblaze processor as well?

 

Thanks again!

 

Keegan

 

 

 

 

 

0 Kudos
Visitor keeganrm
Visitor
6,321 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

So I've made some progress on my issue. First of all, it seems that I had tried to use the Chip Enable port on the EMC (instead of the Active-Low Chip Enable port). I fixed that because the asynchronous mode only uses CEN, and I also updated the EMC configuration with a base address similar to the base address that I specified in the AXI crossbar switch.

 

I re-ran the same test as before (read all registers from 0x80000000 and up) and I got data responses this time, but the same thing happened again when I got to address 0x8000003C (which is the base + 0x3C). 

 

When I read from 0x8000003C, I got an initial data response, but the EMC's AXI interface started getting sending more read valid pulses again (along with more data). 

 

I'm still attempting to characterize the behavior, but it seems like when I read from that address (Base Address + 0x3C), the flash sends the data from that address, but then automatically starts sending more data, without provocation from my design. The data capture (from the Xilinx ILA) shows the pulse strobing 16 times (but it might keep going if the data window were larger), and for the first 8 strobes, new data is driven onto the rdata AXI port, then for the last 8 stobes, all zeros are on the rdata port. I've attached the ILA data file, just in case I'm doing a bad job explaining what's going on.

 

Is there some configuration for the Flash memory on the VC707 or the EMC core itself that is triggering this?

 

0 Kudos
Scholar pratham
Scholar
6,265 Views
Registered: ‎06-05-2013

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@keeganrmYes, the design uses a MicroBlaze and an AXI EMC. I have sent a design from the FTP, please check your email.

I hope this will help.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Visitor keeganrm
Visitor
6,227 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@pratham Thanks for sending me the reference design. 

 

I notice that the timing parameters in your EMC configuration are in fact different from mine. I took my timing parameters from the Micron datasheet for the PC28F00AG18FE, as instructed by the AXI EMC user guide (PG100). Is there any reason why there is this inconsistency? 

 

There are three differences between our timing configurations (yours/mine):

tPACC (or tAPA) - Page Access Period (ns): 25000 / 15000

tEHOZ - Read CE High to Data Bus HZ Period (ns): 9000 / 7000

tGHOZ - Read OE High to Data Bus HZ Period (ns): 9000 / 7000

 

If your timing parameters are correct (as I would assume, because your tests passed), shouldn't there be some documentation of this inconsistency, so that users of the VC707 know how to configure the EMC core later? 

0 Kudos
Scholar pratham
Scholar
6,217 Views
Registered: ‎06-05-2013

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@keeganrm I agree. I will write an AR on this.

Use the design's parameter and let me know if it helps you.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Visitor keeganrm
Visitor
6,207 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@pratham After a bit more research on the Micron Flash part that's on the VC707 (P/N:PC28F00AG18FE) and a bit more testing in my lab, I finally got an expected response from the flash - and this is before I've made any changes to the timing parameters.

 

The difference between my timing parameters and the timing parameters of your design are minimal, and your timing parameters seem to be a little more lax than mine are, so I wonder if both actually work. 

 

The only test I have successfully completed was issuing the Read Status Register Command to the flash, and it returned the default value of 0x0080. I'm going to try to do some more testing with my card to confirm that everything is working. It would be easier if I understood this flash interface better, but I'm learning.

 

If my tests are successful with my own timing parameters (as listed in my previous posts), I'm not sure which parameters should be used in the Answer Record - though I do think that it would be useful to have an AR to make it clear what timing parameters should be used for either Synchronous reads or Asynchronous reads. Also, another useful bit of information would be what clock speeds the AXI clock and the RDCLK can run at for both configurations (because that wasn't very clear either when I was looking in the PG100 AXI EMC Product Guide). 

 

I'll post again after some testing.

 

Thanks again for your help,

 

Keegan

 

0 Kudos
Visitor keeganrm
Visitor
6,015 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

After synthesis, I notice that the EMC core tied the adv_ldn (address valid/load new address) pin to ground. Is there any way to configure the core so that the pin will latch the address bus like it's supposed to (while still keeping a valid configuration for Asynchronous read mode)?

 

0 Kudos
Scholar pratham
Scholar
3,949 Views
Registered: ‎06-05-2013

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@keeganrm Two things

 

1) Timing parameters are taken from datasheet which is used in the design I sent

2) ADV_B low is valid for sync and async mode of the flash. You cannot customize the IP to change the ADV_B connection.

 

Check the image attached which is taken from VC707 BPI flash family datasheet.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
forum.JPG
Visitor keeganrm
Visitor
8,743 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

@pratham Thanks for the response. I now understand why the EMC core ends up tying ADV# to ground, but this limits the functionality of the IP core, as ADV# is used to latch the upper-order bits of the address bus, so that the Asynchronous page read mode can be utilized.

 

That being said, I'm not trying to use the buffered-page read mode, I'm trying to configure the EMC to use single-beat AXI transactions, so I have no use for the ADV# pin. 

 

As I'm trying to set it up for single beat transactions, I statically set the following ports: 

axi_a*burst => "01" , -- increment burst type
axi_a*size => "001" , -- 2 bytes per transfer (because the flash is a 16-bit bus)

 

With those read/write AXI ports set statically, and the AXI read/write length (axi_a*len) set to X"00", the each AXI read/write transaction should be a single-beat with 2 bytes, correct? 

 

I'm still having an issue with the core though, because my AXI write requests to the EMC IP seem to cause the flash address bus to increment four times. When I attempt to write the Read Status Register command to the EMC core at address 0x81020000, I see the address bus first get set to 0x81020000, then 0x81020002, 0x81020004, and 0x81020006, then back to 0x81020000. On each address transition I also see that CEN toggles (so the EMC core is writing the Read Status Register Command to four different addresses each time I want to only write to one).

 

I had the same issue with the incrementing address during AXI read requests, before I configured the AXI ports as I described above. When I updated the AXI ports to statically set them to the values above, the address no longer incremented four times during the read, instead the address bus stayed the same during the entire transaction.

 

I have the same configuration on both arburst/awbust and arsize/awsize, yet I'm now only seeing this issue during the write request, so I'm not really sure where to go from here. 

 

 

 

0 Kudos
Visitor keeganrm
Visitor
3,893 Views
Registered: ‎01-17-2017

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

I've figured out the cause to the multi-write issues I was having. I had the WSTRB port statically set to 0xFF, so that was causing the EMC core to generate a write to flash for each 16-bit word in my 64-bit data field (causing the address to increment 4 times). I was only intending to enable the first 16-bits of the 64-bit data bus, so I now have set the WSTRB to 0x03, and now only a single-beat, 16-bit, transaction takes place during my write requests to flash.

 

The problem I had with multiple reads during a single read transaction was fixed by setting a*size to 0b001 (2-byte transfer), and making sure a*len is set to 0x00 (single-beat transaction) during the read transaction.

 

@pratham I never had to change my EMC timing parameters from my first post (but I have the flash interface working), and so I was wondering if we could get the inconsistency addressed. 

 

There are only three differences between our timing configurations (yours/mine):

tPACC (or tAPA) - Page Access Period (ns): 25000 / 15000

tEHOZ - Read CE High to Data Bus HZ Period (ns): 9000 / 7000

tGHOZ - Read OE High to Data Bus HZ Period (ns): 9000 / 7000

 

The datasheet that I have from Micron is "256-512mb_1gb_65nm_g18_it.pdf - Rev. I 05/15 EN" (read from the footer of the document). I've included my copy that I recently received from Micron's NOR flash support.  

 

 

0 Kudos
Observer gsxftxx
Observer
1,794 Views
Registered: ‎03-06-2018

Re: VC707 BPI Flash Access using AXI EMC

Jump to solution

Hi @keeganrm  I'm experiencing similar problem, when I'm trying to read flash through AXI EMC, I lost half of the data, which seems like EMC is trying to read 32 bits each time, while flash is 16 bits. I then found this post, but cannot figure out how to set this:

axi_a*burst => "01" , -- increment burst type
axi_a*size => "001" , -- 2 bytes per transfer (because the flash is a 16-bit bus)

wondering if anybody can give me a hint?

 

0 Kudos