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Visitor
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Registered: ‎11-05-2020

VHDL CODE ERRORS

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rfid is

Port ( clk : in  STD_LOGIC;

apwd : in  STD_LOGIC_VECTOR (31 downto 0);

kpwd : in  STD_LOGIC_VECTOR (31 downto 0);

rt1 : in  STD_LOGIC_VECTOR (15 downto 0);

rt2 : in  STD_LOGIC_VECTOR (15 downto 0);

rt3 : in  STD_LOGIC_VECTOR (15 downto 0);

rt4 : in  STD_LOGIC_VECTOR (15 downto 0);

rm1 : in  STD_LOGIC_VECTOR (15 downto 0);

rm2 : in  STD_LOGIC_VECTOR (15 downto 0);

rm3 : in  STD_LOGIC_VECTOR (15 downto 0);

rm4 : in  STD_LOGIC_VECTOR (15 downto 0);

xorouts : out  STD_LOGIC_VECTOR (15 downto 0));

end rfid;

architecture Behavioral of rfid is

component randsel is

Port ( clk:in std_logic;

r1 : in  STD_LOGIC_VECTOR (15 downto 0);

r2 : in  STD_LOGIC_VECTOR (15 downto 0);

r3 : in  STD_LOGIC_VECTOR (15 downto 0);

r4 : in  STD_LOGIC_VECTOR (15 downto 0);

m1 : in  STD_LOGIC_VECTOR (15 downto 0);

m2 : in  STD_LOGIC_VECTOR (15 downto 0);

m3 : in  STD_LOGIC_VECTOR (15 downto 0);

m4 : in  STD_LOGIC_VECTOR (15 downto 0);

counts:in integer range 0 to 9;

rtx : out  STD_LOGIC_VECTOR (15 downto 0);

rmx : out  STD_LOGIC_VECTOR (15 downto 0));

end component;

component apwpad is

Port (--clk:in std_logic;

apwd : in  STD_LOGIC_VECTOR (31 downto 0);

rt : in  STD_LOGIC_VECTOR (15 downto 0);

rm : in  STD_LOGIC_VECTOR (15 downto 0);

kpwd : in  STD_LOGIC_VECTOR (31 downto 0);

padx : out  STD_LOGIC_VECTOR (15 downto 0));

end component;

component xorr is

Port ( ain : in  STD_LOGIC_VECTOR (15 downto 0);

bin : in  STD_LOGIC_VECTOR (15 downto 0);

cout : out  STD_LOGIC_VECTOR (15 downto 0));

end component;

component mux4 is

Port ( ain : in  STD_LOGIC_VECTOR (15 downto 0);

bin : in  STD_LOGIC_VECTOR (15 downto 0);

cin : in  STD_LOGIC_VECTOR (15 downto 0);

din : in  STD_LOGIC_VECTOR (15 downto 0);

cntr : in  STD_LOGIC_VECTOR (1 downto 0);

outm : out  STD_LOGIC_VECTOR (15 downto 0));

end component;

signal rtx,rmx :std_logic_vector(15 downto 0);

signal apwdl,apwdm,ccpwdl,ccpwdm,msout,padx,xorout:std_logic_vector(15downto 0);

signal cntrl:std_logic_vector(1 downto 0);

signal count :integer range 0 to 9 := 0;

begin

r0:randsel port map(clk,rt1,rt2,rt3,rt4,rm1,rm2,rm3,rm4,count,rtx,rmx);

ap0:apwpad port map(apwd,rtx,rmx,kpwd,padx);

m4:mux4 port map(apwdm,apwdl,ccpwdm,ccpwdl,cntrl,msout);

x0:xorr port map(padx,msout,xorout);

process(clk)

begin

if(clk'event and clk = '1')then

xorouts <= xorout;

if(count = 0)then

--rtx <= rt1;

--rmx <= rm1;

apwdm <= apwd(31 downto 16);

apwdl <= apwd(15 downto 0);

ccpwdm <= "0000000000000000";

ccpwdl <= "0000000000000000";

cntrl <= "00";

elsif(count = 1)then

--rtx <= rt2;

--rmx <= rm2;

cntrl <= "01";

ccpwdm <= xorout;

elsif(count = 2)then

--rtx <= rt1;

--rmx <= rm1;

cntrl <= "10";

ccpwdl <= xorout;

elsif(count = 3)then

--rtx <= rt2;

--rmx <= rm2;

cntrl <= "11";

apwdm <= xorout;

elsif(count = 4)then

--rtx <= rt3;

--rmx <= rm3;

cntrl <= "00";

apwdl <= xorout;

elsif(count = 5)then

--rtx <= rt4;

--rmx <= rm4;

cntrl <= "01";

ccpwdm <= xorout;

elsif(count = 6)then

--rtx <= rt3;

--rmx <= rm4;

cntrl <= "10";

ccpwdl <= xorout;

elsif(count = 7)then

--rtx <= rt4;

--rmx <= rm4;

cntrl <= "11";

apwdm <= xorout;

elsif(count = 8)then

apwdl <= xorout;

end if;

count <= count + 1;

end if;

end process;

end Behavioral;

 

I am running this code using a spartan-3E starter board in Xilinx Ise but while running I am getting an error If anyone could solve this I would be very thankful.

Error1:Xst:752 - "C:/Users/Acer/RFIDAUTHENTICATION/rfid.vhd" line 61: Unconnected input port 'clk' of component 'apwpad' is tied to default value.

Error2:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

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Teacher
Teacher
444 Views
Registered: ‎07-09-2009
sorry , that is totaly un redable.

Can you upload it as code, or as an attachment please.

just a quciky,
dont use if(clk'event and clk = '1') , use if rising_edge( clk )

Dont use IEEE.STD_LOGIC_ARITH.ALL;IEEE.STD_LOGIC_UNSIGNED.ALL;

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Highlighted
Teacher
Teacher
445 Views
Registered: ‎07-09-2009
sorry , that is totaly un redable.

Can you upload it as code, or as an attachment please.

just a quciky,
dont use if(clk'event and clk = '1') , use if rising_edge( clk )

Dont use IEEE.STD_LOGIC_ARITH.ALL;IEEE.STD_LOGIC_UNSIGNED.ALL;

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Contributor
Contributor
385 Views
Registered: ‎11-25-2019

Hi @Manisha28,

 

I do not know your exact design but what I understand from the error is that you forgot to connect "clk" port of "apwpad" module in this module called "rfid".

If you declare a port in a module and if you call module in another module, you should connect every port to something. So, if you do not want to use "clk" port of "apwpad" module, get rid of "clk" port declaration in "apwpad" module. If you want to use it, please connect the port in "rfid" module.

 

Good luck.

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Visitor
Visitor
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Registered: ‎11-05-2020
I don't want to use the clock in apwpad module but there is a clock in all other modules like kpwd,rt1,xorr,mux4, etc sir how to initialize it could you say according to the above code sir, I am new to VHDL sir please help me I would be very thankful,
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Teacher
Teacher
331 Views
Registered: ‎07-09-2009

wow,

thats got no formating at all !!

 

Thsi could be the error,

process(clk)
begin
         if (clk'event and clk = '1')then
             xorouts <= xorout;
         if  (count = 0)then

 

The second if should be an elsif 

try the code with formatting , and re post,

 

 

 

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Visitor
Visitor
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Registered: ‎11-05-2020
No sir nothing changed
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Visitor
Visitor
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Registered: ‎11-05-2020
Sir I have runned the code in Xilinx ISE design suite how can I futher implement it using chipscope
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Contributor
Contributor
296 Views
Registered: ‎11-25-2019

Hi @Manisha28,

I think you should first debug your code with "testbench" or something else because there are many latch conditions and there are many registers that are not used in anywhere like "outint" in module "decimalconver". 

Also, you should name your variables, registers and ports with understandable names. You should have an order while coding. There are many resources on internet about how to indent your code, how to name your variables etc.

If you do not be careful about these points, we cannot help you fast.

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Teacher
Teacher
237 Views
Registered: ‎07-09-2009
You have multiple errors,
till you find the last one, you will have errors.

Format the code , use a txt editor that recognises VHDL such as notepad++
then, realise you do not need to have the component declarations, nor the clk'event ,

and then come back to us,

Can I recommend a free book to reference, read and digest.

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf



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Highlighted
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Registered: ‎06-21-2017

You cannot use chipscope until your design synthesizes and builds.  You can try to simulate, but if you have syntax errors, you cannot simulate either.  Compiling for simulation will produce different error messages that may be more understandable to you. 

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