11-22-2020 08:40 AM
Hello, I am running the below code in XILINX ISE DESIGN SUITE 14.7 version,
I am using xc3s500e-4fg320 board for running the VHDL code,
The syntax everything is correct but I am getting output signal as 00000,
I don't know why I am getting all zeros as output,
Please help me to get the correct output,
I would be very grateful if anyone could find what is the error
11-22-2020 08:59 AM
11-22-2020 09:45 AM
I just looked at your testbench and I really do not know what your code is doing but I think the problem is that you give zeros to all of your inputs (like rt1, rt2... etc.) in the testbench module. Are these signals supposed to be like that? Good luck.
11-23-2020 06:44 AM
Normally, this is where you debug the design.
Usually, start from the output, follow the outputs back - are the output sources 0? then are their sources what you expect? and follow it all the way back to the input. This is how to debug in a simulator.
If it compiles and runs, the assuming all source code for components is present, then there is a problem in the testbench or the design.
11-23-2020 06:59 AM