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Visitor
Visitor
293 Views
Registered: ‎11-05-2020

VHDL CODE SIMULTION ERROR

Hello, I am running the below code in XILINX ISE DESIGN SUITE 14.7 version,

I am using xc3s500e-4fg320 board for running the VHDL code,

The syntax everything is correct but I am getting output signal as 00000,

I don't know why I am getting all zeros as output,

Please help me to get the correct output, 

I would be very grateful if anyone could find what is the error

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8 Replies
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Teacher
Teacher
280 Views
Registered: ‎07-09-2009

so what is the error ?
how long have you run the simulation ?
What warnings are you getting ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
265 Views
Registered: ‎11-25-2019

Hi @Manisha28,

I just looked at your testbench and I really do not know what your code is doing but I think the problem is that you give zeros to all of your inputs (like rt1, rt2... etc.) in the testbench module. Are these signals supposed to be like that? Good luck.

Yunus,

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Visitor
Visitor
188 Views
Registered: ‎11-05-2020

There were no errors sir, but I am not getting the output signal
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Visitor
Visitor
187 Views
Registered: ‎11-05-2020

The test bench is automatically generated by XILINX ISE DESIGN SUITE sir , I haven't changed anything
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Scholar
Scholar
174 Views
Registered: ‎08-01-2012

Normally, this is where you debug the design.

Usually, start from the output, follow the outputs back - are the output sources 0? then are their sources what you expect? and follow it all the way back to the input. This is how to debug in a simulator.

If it compiles and runs, the assuming all source code for components is present, then there is a problem in the testbench or the design.

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Teacher
Teacher
166 Views
Registered: ‎07-09-2009

Have a look at the test bench code.
The test bench automatically generated, has no idea as to what inputs you want up or down when. It is just the basis you add you bits to.

Try this book for reference

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

https://vhdlguide.readthedocs.io/en/latest/vhdl/testbench.html


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Visitor
Visitor
155 Views
Registered: ‎11-05-2020

THANKS FOR THE REPLY SIR
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Visitor
Visitor
152 Views
Registered: ‎11-05-2020

ok sir thank you
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