VHDL CODE SIMULTION ERROR

[Manisha28]

Hello, I am running the below code in XILINX ISE DESIGN SUITE 14.7 version,

I am using xc3s500e-4fg320 board for running the VHDL code,

The syntax everything is correct but I am getting output signal as 00000,

I don't know why I am getting all zeros as output,

Please help me to get the correct output, 

I would be very grateful if anyone could find what is the error

[drjohnsmith]

so what is the error ?
how long have you run the simulation ?
What warnings are you getting ?

[yunusbaskan]

Hi @Manisha28,

I just looked at your testbench and I really do not know what your code is doing but I think the problem is that you give zeros to all of your inputs (like rt1, rt2... etc.) in the testbench module. Are these signals supposed to be like that? Good luck.

Yunus,

[Manisha28]

There were no errors sir, but I am not getting the output signal

[Manisha28]

The test bench is automatically generated by XILINX ISE DESIGN SUITE sir , I haven't changed anything

[richardhead]

Normally, this is where you debug the design.

Usually, start from the output, follow the outputs back - are the output sources 0? then are their sources what you expect? and follow it all the way back to the input. This is how to debug in a simulator.

If it compiles and runs, the assuming all source code for components is present, then there is a problem in the testbench or the design.

[drjohnsmith]

Have a look at the test bench code.
The test bench automatically generated, has no idea as to what inputs you want up or down when. It is just the basis you add you bits to.

Try this book for reference

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

https://vhdlguide.readthedocs.io/en/latest/vhdl/testbench.html

[Manisha28]

THANKS FOR THE REPLY SIR

[Manisha28]

ok sir thank you