07-27-2021 10:20 AM
I am new to indexing arrays in VHDL and there is a lot of information on online forums on how to access a bit in an element. However how do you access a group of bits in an array element. My guess would have been the following:
type mem is array (0 to 7) of STD_LOGIC_VECTOR(255 downto 0);
signal d_type_register : mem (others => (others => '0'));
d_type_register(0)(127 downto 0) <= (others => '0');
d_type_register(3)(255 downto 0) <= (others => '1');
Is this correct? If not could you respond with the correct syntax please.
07-27-2021 10:47 AM
Your use examples are correct. The second one could just be simply "d_type_register(3) <= (others => '1');". Your initialization in the signal declaration is missing a ":= " between mem and (others).
07-27-2021 12:56 PM
Is this correct? If not could you respond with the correct syntax please
The fastest way someone can answer that for you is the compiler. Just compile and see what happens in you encounter such occasions in the future!
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