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HarryB1
Visitor
Visitor
268 Views
Registered: ‎06-24-2021

VHDL array bit accessing

Hi Everyone, 

I am new to indexing arrays in VHDL and there is a lot of information on online forums on how to access a bit in an element. However how do you access a group of bits in an array element. My guess would have been the following:

declaration:

type mem is array (0 to 7) of STD_LOGIC_VECTOR(255 downto 0); 

signal d_type_register : mem (others => (others => '0'));

 

use examples: 

d_type_register(0)(127 downto 0)  <= (others => '0');

d_type_register(3)(255 downto 0)  <= (others => '1');

 

Is this correct? If not could you respond with the correct syntax please. 

 

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2 Replies
seamusbleu
Voyager
Voyager
253 Views
Registered: ‎08-12-2008

Your use examples are correct.  The second one could just be simply "d_type_register(3) <= (others => '1');".  Your initialization in the signal declaration is missing a ":= " between mem and (others).

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dpaul24
Scholar
Scholar
220 Views
Registered: ‎08-07-2014

@HarryB1 ,

Is this correct? If not could you respond with the correct syntax please

The fastest way someone can answer that for you is the compiler. Just compile and see what happens in you encounter such occasions in the future!

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