VccAux_IO_G "2.0V option for slightly-increased performance at very fastest bit rates" on XC7Z030FFG676 : Interogative GHz

[mjdbishop]

UG471 Chapter 1 VccAux_IO section (p18 in v1.10) states, regarding the voltage supply for VccAux_IO_G0 "The 2.0V option is available when the slightly-increased performance is required for the very fastest bit rates supported for the single-ended drivers."

Some further (contextual) information is provided by UG475, UG865 and DS191.  However, no indication is given of when provision of a 2.0V rather than 1V8 supply to VccAux_IO_G# is appropriate / necessary.  At its simplest how many GHz does "very fastest" correspond to.

a) Can anyone advise from experience or knowledge what the threshold is ?

b) Can the documentation address this point idc

FWIW in the design at issue the single ended IO on banks 33, 34 & 35 is "slow" e.g. 25 MHz clocks, certainly < 100 MHz.

Martin

[mjdbishop]

It seems likely that this 2V issue is primarily associated with DDR3/4 on 7 series FPGAs

The 7Series Schematic Review reccommendations Row 18 regarding VCCAUX_IO_G# say "see UG586" (the Memory Interface Solutions User Guide)

U586 ch 1 ~p34 says "VCCAUX_IO – Set based on the period/frequency setting. 2.0V is required at the
highest frequency settings in the High Performance column. The MIG tool
automatically selects 2.0V when required. Either 1.8 or 2.0V can be used at lower
frequencies."

My inference is that the 2V case primarily arrises when DDR3/4 is attached to the 7 series PL.  An unlikely use case for a Zynq, although quite plausible for an FPGA.

Therefore can anyone confirm that 2V operation is a red herring for DDR on PS and slow(ish) IO on the PL ?

Martin

[gnarahar]

@mjdbishop Its mostly for the DDR interfaces. Take a look at Table 53, 54 in DS191 that shows the data rates for VCCAUX_IO of 2.0V/1.8V. 

This AR would help as well: https://www.xilinx.com/support/answers/42765.html

[mjdbishop · Accepted solution]

@gnarahar Thank you for your clarification and additional document references.

My summary of the situation is:

- VccAux_IO should be 1v8 except where it has to be 2v0 (e.g. for DDR3/3L configured for a 4:1 memory clock on the HP banks of an FF packaged Kintex7 / mid-range Zynq)

- therefore when DDR is not interfaced to the PL / HP banks this consideration does not apply and VccAux_IO should be 1v8

This rabbit chase was started by the 7series checklist, row 18, which states

Supply must be run at 2.0V for high-speed memory applications, but only has a ±3% tolerance. See UG586 "Design Guidelines" and family specific data sheet for voltage tolerances. Also see UG471 for more info on VCCAUX_IO grouping.

May I suggest that this reccomendation is revised to provide a more accurate precis and comprehensive references

Best Regards

Martin