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Explorer
Explorer
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Registered: ‎07-10-2013

Vcco Different From Expected Voltage

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For all FPGA and CPLD devices in general, and specifically for Spartan-3A, Spartan-6 and Spartan-7/Artix-7 devices, what is the result for LVCMOS outputs if the Vcco voltage provided is less than the I/O standard voltage expected?

For example, if an output is configured as LVCMOS3.3, with the Vcco actually connected (whether accidentally or intentionally) being any of 3.1V, 2.8V, 2.5V, 2.0V, or etc., will output properly occur on the output pin?

Similarly for an input configured as LVCMOS3.3, if the input signal swings only between 0V and the actual Vcco voltage applied, will input properly occur?

And, is there an "optimal" LVCMOS specification (perhaps something other than LVCMOS3.3) that should be used for the highest probability of success in allowing either output or input or both to be successful in the face of unexpected/improper Vcco voltages?

In other words, what role does the specified I/O Standard play in getting the hardware to properly perform simple single-ended (not differential) LVCMOS output and input?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @chsdkj 

Xilinx FPGA IO standards are based on specifications defined by Electronic Industry Alliance JEDEC website at: http://www.jedec.org.

Each device datasheet and Select IO user guide specifies VCCO level required for IO standard (For example check Table 1-55:VCCO and VREF Requirements for Each Supported I/O Standard in UG471 (v1.10)). We do not characterize Select IO of our devices at non-recommended VCCO, so we cannot comment on behavior of IO's in such condition. If there is possibility to use VCCO other than mentioned by Xilinx datasheet and Select IO user guide, then we specifically mention it in notes of user guide or Xilinx answer records (For example : Check notes of Table 1-55:VCCO and VREF Requirements for Each Supported I/O Standard in UG471 (v1.10) and https://www.xilinx.com/support/answers/43989.html)

Regards,
Bhushan

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2 Replies
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Registered: ‎06-21-2017

I am not a Xilinx employee nor am I privy to the internals of any of the FPGAs.  In general, with a CMOS output, the output high voltage will drive to a couple hundred millivolts of VCCO.  If you power a LVCMOS3.3 with 3.1 volts, the output high voltage will probably be around 2.8V, that is a schottkey diode drop from VCCO.  This depends on load and drive strength but for a typical digital load is usually close.  If you get further from the VCCO setting, this relationship may fall apart.  Only Xilinx knows and they may not reveal the circuitry.

The input switch point from high to low will probably be around the actual VCCO/2 not the select IO setting.  There are no guarantees exactly where it will be.  Also remember that you cannot drive the input with a signal greater than VCCO, since this may damage the input.  The inputs are diode clamped to VCCO, but these can only handle limited current.

Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎03-07-2018

Hi @chsdkj 

Xilinx FPGA IO standards are based on specifications defined by Electronic Industry Alliance JEDEC website at: http://www.jedec.org.

Each device datasheet and Select IO user guide specifies VCCO level required for IO standard (For example check Table 1-55:VCCO and VREF Requirements for Each Supported I/O Standard in UG471 (v1.10)). We do not characterize Select IO of our devices at non-recommended VCCO, so we cannot comment on behavior of IO's in such condition. If there is possibility to use VCCO other than mentioned by Xilinx datasheet and Select IO user guide, then we specifically mention it in notes of user guide or Xilinx answer records (For example : Check notes of Table 1-55:VCCO and VREF Requirements for Each Supported I/O Standard in UG471 (v1.10) and https://www.xilinx.com/support/answers/43989.html)

Regards,
Bhushan

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