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Registered: ‎08-19-2019

Vhdl clockdivider

Design a Clock divider that divides clock to 2,4,8,16 according to binary input of x i.e.x equals “00”,”01”,”10”,”11”.assume that you have 100 mhz clock frequency

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2 Replies
Registered: ‎04-18-2011

Is this a homework problem that you've just copied and pasted in here?

I doubt your lecturer would take kindly to this approach to completing the assignment...

You'd be better off trying it yourself and then asking for help with a specific problem. 

When I was learning verilog/VHDL I was taught to think of a triangle of 3 things: gates, code and then a timing diagram. 

The idea is if you have the code you should be able to draw the gate level diagram of the circuit and draw the timing diagram. 

If you have the gate level diagram you should be able to draw the timing diagram of the inputs and outputs and write the VHDL that approximates this, and so on...

Start with something like the timing diagram and for each change of the control signal plot the output. 

Look up clock divider using flip flops online and then you should have an idea of the circuit. After this writing the HDL should be straight forward. 

Is this supposed to be implemented in an FPGA? Then extra credit for telling everyone why making a clock divider with flip flops is a bad idea in and FPGA. 


Don’t forget to reply, kudo, and accept as solution.
Registered: ‎07-23-2019

I'll give you some clues, but just a bit:

- with a flip-flop you can divide a clock by two, so with a sequence of them you can have something divided by powers of two

- there is something called mux (multiplexer) that allows you to select 1-of-N signals given some input code

Now it's time for you, look for things, try things out, fall seven times stand up eight (Japanese saying), mum is not going to be there all the time to lift you up