12-14-2017 02:42 PM
I'm doing some HDMI processing with a Zybo Z7-10 board, and I'm using the video mixer to overlay some images on my output screen (1920x1080). I'm loading the images from an sd card, storing as an aligned array, and writing one image to each layer of the video mixer. It seems to work fine for smaller images. However, if I try and draw something that's wider than about 128 pixels, the HDMI output stream crashes when I enable the layer. I can make the image as tall as I want, the issue only seems to be tied to the width. My only thought is that it may be causing a stack overflow, but I don't think that's likely since I'm able to create a large array of zeros and only draw a small portion of it.
12-14-2017 03:41 PM
I guess that the route cause is overflow/underflow issue on fifo or architecture or timing violation issue or issue bandwidth issue for DRAM.
Would you confirm each suspicious item ?
12-15-2017 02:47 PM
Hi watari, thanks for the response. What could I do to check these issues?
I've attached a picture of my block diagram for context. My video mixer has 3 memory layers, no streaming layers, and is connected in series after the video DMA block and before the AXI4-Stream to video out block
The video mixer itself doesn't have a fifo. The video DMA block might have one, but I don't think it's affecting it because the base video stream works fine, I only get problems when I try and draw an image that's too wide. The fifos on the S0x_AXI ports connected to the m_axi_mm_video ports on the video mixer are all disabled, but I don't think that's the issue since I'm only sending commands through these ports.
It might be a DDR clocking issue, since the images are stored in DDR, and their addresses are passed to the video mixer on startup. I'm not sure if the video mixer will copy the images from DDR into its own BRAM and draws it from there, or if it constantly pulls the images directly from DDR.
12-18-2017 07:24 PM
I don't understand meaning of DDR clocking issue.
But I'm palpably sure that the route cause is DRAM bandwidth issue.
I guess the video mixer issues read command via AXI4 to DRAM controller, but it locally stall because of instantaneous bandwidth is failure.
If you fix this issue, it may insert FIFO between v_mix and axi_interconnect to keep instantaneous bandwidth of DRAM.
11-22-2018 06:17 AM
I'm doing similar project, but I don't know how to use the video mixer IP, I have tried many times, it didn't work, I will appreciate it if you sent me your project, I will use it just for learning, thank you so much! My E-mail: firstname.lastname@example.org