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6,290 Views
Registered: ‎11-02-2016

Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

Hi all,

 

is it possible to use one RX channel as clock input to another quad's reference clock for sampling RX data?

 

For a special mode, I would like to use a supplied clock that is being transmitted via an RX channel of one quad to sample the RX data coming in via another quad without any phase correction.

 

From the "7 Series FPGAs GTX/GTH Transceivers User Guide" I have learned that in order for the CDR to lock to reference, I need to set RXCDRHOLD = 1’b1 and RXCDROVRDEN = 1’b0 (p 203). Do I need to externally route the clock signal supplied from another chip to the REFCLK input of the quad I want to sample data from or can I configure another quad's receive channel output to drive the REFCLK of the wanted quad?

 

I can bypass the PLLs (QPLL and CPLLs) to not meddle with the ~600 MHz clock supplied, right? Are there any special requirements for the clock signal as regards frequency, phase noise etc.?

 

 

Thanks for any helpful hints!

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Moderator
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6,281 Views
Registered: ‎07-30-2007

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

You can't use an internal clock as a reference clock.  It is possible to use a reference clock from a nearby quad but not an internally generated clock.  In general a clock from the fpga would require an external PLL chip to "clean it" before it could drive a reference clock input.




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6,276 Views
Registered: ‎11-02-2016

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

So you mean the clock signal that is transmitted via a receive channel would have to exit the FPGA again, be "cleaned" and input to the REFCLK pin of the quad that is receiving the user data?

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6,271 Views
Registered: ‎02-16-2010

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

Yes.
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6,240 Views
Registered: ‎11-02-2016

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

In that case I'd route the external clock signal via a PLL chip to the REFCLK input.

 

Any requirements to the clock signal other than the ones found in the "Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics" on p 56?

 

Thanks.

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6,234 Views
Registered: ‎11-02-2016

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

Using a 600 MHz reference clock, is it possible to bypass all PLLs inside the quad/channel and make CDR lock to reference? Such that the data is being sampled with the reference clock frequency and phase.

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6,203 Views
Registered: ‎07-30-2007

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

I don't think you can bypass all PLL's.  Why would you want to?  The GT will recover a clock from the input signal.  If the signal is not suitable for driving the CDR your best bet would probably be to use oversampling.  Just drive an ordinary asynchronous refclk to the channel and use it to drive the GT in oversampling mode. 




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6,196 Views
Registered: ‎11-02-2016

Re: Virtex-7 GTX: Feeding REFCLK from another RX channel possible?

For a certain test mode, I'd like to use the exact clock as it's supplied (frequency, phase) to sample the data.

 

That's why I would also make CDR lock to reference.

 

Can you please clarify Oversampling Mode?

 

Thanks!

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