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Contributor
Contributor
4,396 Views
Registered: ‎03-07-2013

Virtex 7 IDELAY on clock input causes Duty Cycle distortion?

I am building a DDR bus input that uses IDELAYS for training (find the valid windows and sample point). I must use an IDELAY on the clock input as well, to position edges appropriately.  PLL is not an option because the clock stops and starts.  My problem is the clock with IDELAY on the input is sufferring bad duty cycle distortion inside the FPGA.  This is revealed by observing circuit operation in chipscope as well as by looking at the clock at an output.  Removing the IDELAY at the clock input fixes the duty cycle distortion.  I have IBUFGDS receiving the differential clock, which feeds an IDELAYE2, which feeds a GBUF.  Clock frequency is 335 MHz.  IDELAY Ref clock frequency is 300 MHz.   Any ideas what may be going wrong and can I fix this?   PN is  XC7VX485T-2FFG1157C.  - Paul Taddonio

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Professor
Professor
4,374 Views
Registered: ‎08-14-2007

One thing you could try is to use an IBUFGDS_DIFF_OUT and create two clocks

from its O and OB outputs instead of using both edges of one clock.  Theoretically the

IDELAY distortion would be matched between the two clocks and the rising edges

would be 180 degrees out of phase after the delay.  That is assuming that the input

clock has a 50% duty cycle.

-- Gabor
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Xilinx Employee
Xilinx Employee
4,370 Views
Registered: ‎06-20-2008

The route from the .O pin through the IDELAY will use a dedicated clock route to any of the clock components.

The route from the .OB pin through the IDELAY will not have a dedicated route so there would be no way to match the delay of the 2 clocks at least in the Virtex families. Also since the route from the N-side does not have a dedicated resource this half of the clock would route through fabric and add some additional distortion to the N-Side.

 

This technique does can be sued successfully in Spartan-6 architectures since all GCLK pads can have routes to clock components.

 

 

 

 

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Contributor
Contributor
4,362 Views
Registered: ‎03-07-2013

Thanks Lyman and Gabor for your responses.  I have resolved this issue, mostly by looking at the Xilinx FPGA Editor. The duty cycle problem was due to the clock routing on non-dedicated routes. That happened because of an unfortunate tool placement of the GBUF in this situation (using an IDELAY on the clock). I manually placed the GBUF in the right spot to receive the dedicated clock route and that works.  It has routed on the dedicated resource.

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