UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor zekken_
Visitor
797 Views
Registered: ‎10-09-2018

Virtex 7 JTAG pins

Jump to solution

Hello everyone!

 

I am new into the FPGA world, but I really like the idea of being able to test my RTL on a real hardware. So first of all, sorry if the question I am going to make is too basic.

 

Right now I do have access to a Xilinx VC709 from my university. My final target is to test a really simple core using this FPGA. In order to debug this core written in HDL I plan to use a debug module IP which happens to have a JTAG interface (tck, tms, trst, tdi, tdo).

 

I checked the schematics of my board and these ports are connected to the BANK0 on the pins T10 (tdi), P11 (tms), P10 (tck), R10 (tdo), however, when I try to synthesize the design, Vivado outputs these warnings:

 

CRITICAL WARNING: [Common 17-69] Command failed: 'T10' is not a valid site or package pin name.
CRITICAL WARNING: [Common 17-69] Command failed: 'P11' is not a valid site or package pin name. 
CRITICAL WARNING: [Common 17-69] Command failed: 'P10' is not a valid site or package pin name. 
CRITICAL WARNING: [Common 17-69] Command failed: 'R10' is not a valid site or package pin name.

 

Seeing these errors I assume that the BANK0 pins are not accessible from the PL, correct?

 

On the other hand, I found this cable Olimex ARM-USB-TINY-H, which is exactly what I am looking for but I do not see a way to connect the 2x10pin connector to my board, is there any way to connect this cable to my board and access the connector pins from the FPGA?

 

The final goal is to execute a really simple program on a CPU core (running on the FPGA) using OCD and GDB.

 

Thank you very much,

 

zekken

0 Kudos
1 Solution

Accepted Solutions
Scholar u4223374
Scholar
739 Views
Registered: ‎04-26-2015

Re: Virtex 7 JTAG pins

Jump to solution

@zekken_ Right, now I understand what you're doing. What you need is essentially a group of I/O pins that you can define as being "processor JTAG interface", and plug the Olimex JTAG adaptor into that. For relatively low-speed JTAG, these pins can be almost any non-dedicated pins on the chip.

 

Based on that, I'd get something like the XM105 FMC breakout card (or this), and pick 20 pins on that to be your JTAG interface. You'll probably have to wire up a custom cable for the Olimex adaptor (you won't be able to match the standard JTAG pinout), but this should not be hard with 0.1" headers.

5 Replies
Scholar u4223374
Scholar
784 Views
Registered: ‎04-26-2015

Re: Virtex 7 JTAG pins

Jump to solution

Vivado includes an Integrated Logic Analyzer core (ILA) for debugging circuits. When that's set up, it's accessible over the standard JTAG interface (which is then accessible over USB on all of the Xilinx boards).

Xilinx Employee
Xilinx Employee
763 Views
Registered: ‎06-02-2017

回复: Virtex 7 JTAG pins

Jump to solution

Hi zekken_,

 

Firstly, JTAG pins are dedicated pins for FPGA, they cannot be used or assigned in the customized logic. That's why the critical warning messages occur.

Generally, JTAG provides two functions, one is to download the bit file into FPGA and the other is used to debug the FPGA logic on-the-fly(I think this is what you want). As you used the VC709 board, the JTAG circuit is designed on the board, the only thing you need to do is install the driver and connect the usb cable between the PC and USB JTAG interface on the board, then you can access the JTAG by vivado tools.

As u4223374 mentioned, if you want to debug your logic module, add the ila into the design, then you can use vivado to debug it. Pls refer to this document: UG936 Lab7 as your reference.

-------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------------------------------------------------------------------------------------------------
Highlighted
Visitor zekken_
Visitor
746 Views
Registered: ‎10-09-2018

Re: Virtex 7 JTAG pins

Jump to solution
Thank you both! The idea is that I have a CPU written in HDL and I want to test a C code (for example) on my design. The debug unit is not to debug the FPGA logic but the C code running on my CPU (which is running on the FPGA). The debug module I have is capable to interact with my CPU design (e.g. set registers, access memory, change the program counter...) but the module has JTAG input ports.

So as zhiq mentioned, I cannot connect the debug module to the current JTAG ports of the FPGA because those are dedicated pins (makes a lot of sense to me), so the best way to achieve what I want (I think) is to use the Olimex cable which is compatible with OCD. However the connector is JTAG 2x10 pin, but I cannot see any connector like this one in my board. Is there any way to connect it to my board? Like using an accesory? Or should I look for another board?

Thank you,
zekken

PS: I will definitely check ILA. I think it will be really useful for my project too.
0 Kudos
Scholar u4223374
Scholar
740 Views
Registered: ‎04-26-2015

Re: Virtex 7 JTAG pins

Jump to solution

@zekken_ Right, now I understand what you're doing. What you need is essentially a group of I/O pins that you can define as being "processor JTAG interface", and plug the Olimex JTAG adaptor into that. For relatively low-speed JTAG, these pins can be almost any non-dedicated pins on the chip.

 

Based on that, I'd get something like the XM105 FMC breakout card (or this), and pick 20 pins on that to be your JTAG interface. You'll probably have to wire up a custom cable for the Olimex adaptor (you won't be able to match the standard JTAG pinout), but this should not be hard with 0.1" headers.

Visitor zekken_
Visitor
632 Views
Registered: ‎10-09-2018

Re: Virtex 7 JTAG pins

Jump to solution

Hi again!

 

Sorry for writing a new post when a previous post has already been marked as the solution, but I found in Google the BSCANE2 device (https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/7series_hdl.pdfPg 73), which seems to do what I was looking for in the original post.

 

I instantiated this module on my design and connected the JTAG pins following the PDF of the link, but when I connect the FPGA and after I program it, in Vivado I can only see the XADC (System Monitor), not the BSCANE2 I connected to the JTAG chain. Is it normal? I am missing something?

 

Thank you,

Ying

 

 

0 Kudos