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Contributor
Contributor
3,959 Views
Registered: ‎10-01-2010

Virtex-7 MMCME2 DRP POWER register issues

I am having issues with the DRP POWER register in the Virtex-7 MMCME2 (address 0x28). This is the least documented register in the corresponding XAPP888. This app note simply states that POWER must be set to 0xFFFF during reconfiguration, but doesn't say how it should be set afterwards. The reference design writes 0xFFFF to this register at the start of a DRP cycle then writes 0x0000 at the end. This last part is not correct. I tried preserving the original POWER setting, then writing it back at the end, but even this is not sufficient in all cases. It appears the POWER setting also depends on the intended CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F values. Here is how I discovered this:

 

I set the MMCME2 parameters in RTL to MULT_F = 32.0 and DIVIDE_F = 4.0 and synthesized the design. I then tried to write a DRP sequence corresponding to MULT_F = 25.5 and DIVIDE_F = 3.125 (using the algorithm in the reference design) and looked at the DRP sequence in ChipScope, which shows the POWER register reading back 0x0100 at the start. I see that the DRP starts off writing POWER with 0xFFFF, then writing back 0x0100, but afterwards the MMCM does not achieve lock (LOCKED never goes high).

 

On the other hand, if I set MULT_F = 25.5 and DIVIDE_F = 3.125 in the RTL, the MMCM powers up fine and achieves lock. I then try to program the exact same DRP sequence corresponding to these parameters. I verify in ChipScope that the values I read from each of the DRP registers are exactly equal to the settings I've calculated for 25.5/3.125, so I know I've calculated them correctly. In this case, the MMCM reacquires lock. I find here that the POWER register's power-on state is 0x9900 (rather than 0x0100 in the 32.0/4.0 case); this tells me that the POWER setting as well is dependent on the MULT_F and DIVIDE_F.

 

Is there a reference I can find that better documents the POWER register? I'd hate to have to figure this out empirically by synthesizing the MMCM for all MULT_F and DIVIDE_F combinations I need. I'm thinking of just leaving the POWER register at 0xFFFF but I don't know what detrimental effect that may have.

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5 Replies
Contributor
Contributor
3,838 Views
Registered: ‎10-01-2010

Re: Virtex-7 MMCME2 DRP POWER register issues

Base on exhaustive testing of different POWER settings with different MULT_F/DIVIDE_F combinations, I've made the following conclusions:

 

  • If MULT_F and DIVIDE_F are both integers, the POWER setting should be 0x0100.
  • If MULT_F and DIVIDE_F are divisible by .500 (but are not both integers), the POWER setting should be 0x1100.
  • For all other combinations, the POWER setting should be 0x9900.

I've asked Xilinx support about this but it seems this register is as mysterious to them as to anyone else. Hope this helps others!

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Visitor oakley
Visitor
2,693 Views
Registered: ‎02-22-2014

Re: Virtex-7 MMCME2 DRP POWER register issues

I am running into the same problem.  I too would like some signal from Xilinx support stating if this is the correct approach to the POWER register.

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Xilinx Employee
Xilinx Employee
2,684 Views
Registered: ‎10-11-2007

Re: Virtex-7 MMCME2 DRP POWER register issues

You shouldn't touch the power bits. They manipulate the internal regulators. If the MMCM doesn't LOCK after a change via the DRP it's more likely that you are violating a spec now. For example, if the Mult value is changed the VCO frequency may be out of spec.

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Explorer
Explorer
1,633 Views
Registered: ‎05-12-2011

Re: Virtex-7 MMCME2 DRP POWER register issues

@ralfk  would you please clarify your response a bit?

 

With regard to the power register, XAPP888 V1.7 page 9 table 14 states: "These bits must all be set High when performing DRP."

The code provided with the XAPP indeed does first set all bits high, and as the last step it sets them all low.

 

My own experience matches that of the original poster, namely that setting the power register to all zero as done in the XAPP code results in the MMCM never locking to anything, ever.  This is on an Artix-7 device.  By examining the contents of the power register for various statically configured MMCMs it's apparent there are different power register settings for different combinations of at least master divide and master multiply.

 

The clarification I request is, if as you say the power bits should NOT be touched, does that mean that we should NOT set the power register bits to all high and as we program the various registers the DRP circuitry automatically configures the correct power settings and we should also omit the final write of all zero?  Or does it mean the power register bits should always remain as they were initially set by whatever static configuration was employed and should never be changed regardless of whether or not the new dynamically configured settings require different values and it will just work out?

 

It would be helpful to learn what SHOULD be done, not what SHOULD NOT be done.  And along that line, I would appreciate it if some kind soul would take a look at whatever code assigns the power register values when synthesizing the instantiation of an MMCM primitive for an Artix-7 device and could boil it down into (hopefully) simple selection criteria for me (and everyone else) so I don't need to synthesize each and every possible configuration I may ever want to use and dig the proper settings out with the ILA (assuming of course that I do indeed need to set the power register to something as all zero does not work).

 

Cheers,

-Doug

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Xilinx Employee
Xilinx Employee
1,604 Views
Registered: ‎10-11-2007

Re: Virtex-7 MMCME2 DRP POWER register issues

Bad choice of words perhaps. Follow the app and set them all high. This is what the wizard will do as well. Vivado uses them to do some power optimization, but if you change things inside the MMCM/PLL via DRP then they need to be all turned on.

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