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cbemlahe
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Registered: ‎09-18-2007

Virtex 7 XADC Channel Sequencer - Understanding the Conversions

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I have a Virtex7 design with the XADC channel sequencer (Wizard Core 3.3). My understanding is that in AXI streaming mode, it continually samples the selected channels and outputs them on an AXI streaming interface. That is indeed what it looks to be doing. I write this data into a small dual port RAM using the AXI_TID as the RAM write address and the AXI_TVALID_S as the RAM write enable.

My micro-controller can then read the dual port RAM (results listed below). The values are changing by several LSBs so they look like ADC conversions to me. My questions are:

1. How do I tie up the AXI output/my results to specific ADC channels (temperature, VCCINT etc)? I expected the values I ticked in the XADC GUI to be cycled around by the sequencer.

2. How do I convert the temperature and voltages? I saw a formula for the temperature conversion but not voltage.

3. The above temperature formula (Equation 1-2 from V7/Zynq UG480) did not give a sensible number. If the ADC is 12 bit, how come the values returned from the AXI are > 12 bit?

ie, AXI_TID=0  has data value of 0x96CE. That is 40046 decimal, which is about what I see reported from the microcontroller.

 

4. How come the AXI is wrapping round to AXI_TID[4:0]=0x1F when there are only 24 channels in total? (I've not looked for gaps in the TID address being output). I've asked for 16 external inputs and 4 internals + calibration. Interestingly below I see the last 16 entries with data and 4 others. These are most likely my selected channel, but was expecting 5 internals (4+calibration).

 

Thanks

David

 

 

 XADC_2.JPGXADC_1.JPG

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cbemlahe
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Registered: ‎09-18-2007

OK, reading more of UG480, I think I'm good. 12 ADC result from core is in bits [15:4]. Bits [3:0] are status bits. The channels are defined in figure 3.1 and the AXI TID output by the core is this ID. All makes sense. 

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cbemlahe
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Registered: ‎09-18-2007

OK, reading more of UG480, I think I'm good. 12 ADC result from core is in bits [15:4]. Bits [3:0] are status bits. The channels are defined in figure 3.1 and the AXI TID output by the core is this ID. All makes sense. 

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