08-13-2012 09:33 AM
i want to know "switch matrix" architecture in vertix-7 and i want to know what the difference between switch matrix in virtex-7 and switch box in older FPGAs
08-13-2012 09:45 AM
Well, you can look in FPGA_Editor. Remember that FPGA_Editor is a software programmer's fantasy of what the hardware looks like, so do not take it literally.
08-13-2012 10:18 AM
We should probably ask what it is that the customer is concerned about. There is a lot of detail in the "bowls" of interconnect and input muxing which the customer wouldn't understand if we simply give them engineering style explanations. And they shouldn't really care about those anyway.
08-13-2012 11:40 AM
Is the question how SLRs interconnect and thus CLBs from one SLR are routed to CLBs on another SLR? Then the short answer is that SLLs do not connect directly to CLBs. SLLs do not span the entire SLRs, only the top/bottom reagions in a staggered fashion. You can find information about how SLRs are interconnected in the below.
08-13-2012 11:53 AM
08-13-2012 05:39 PM
i want to know how SLRs are connected to each other with SLL clearly for routing in physical design. for example in 3d FPGA layers are connected by TSVs and 3d Switch box but i don't know in this device how SLRs are connected to each other. Can you send me a figure that show how SLRs connected to each other . and i want to know what is the role of switch matrix in this device because in FPGA editors show that vertical long lines are connected to this switch matrix but i don't know why?
08-17-2012 05:51 AM
08-17-2012 08:51 AM
There are many places to find architecture information,
Look at patents at the USPTO.
Look at papers published at conferences:
along with papers on ACM, and IEEE.
Look at the Xilinx documentation.
Bascially, we have no interest in helping with your research: you have to do it, all by yourself (no one will do it for you). This presumes you are a student, and you have either chosen to do this, or was assigned it to do.
If this is a commercial application, a call to your local Xilinx Field Applications Engineer (FAE) will get all your questions answered.
08-28-2012 02:53 PM
my project is about developing a three dimensional physical design tool (TPR) based on SSI technology. thus for routing
and placement, i need information about how to connect SLRs by SLLs that i cannot find it in Xilinx 's documentation.
who can help me?