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Visitor
Visitor
8,658 Views
Registered: ‎08-12-2012

Virtex-7 architecture

i want to know "switch matrix" architecture in vertix-7  and i want to know what the difference between switch matrix in virtex-7 and switch box in older FPGAs

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Scholar
Scholar
8,657 Views
Registered: ‎02-27-2008

e,

 

Well, you can look in FPGA_Editor.  Remember that FPGA_Editor is a software programmer's fantasy of what the hardware looks like, so do not take it literally.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
8,650 Views
Registered: ‎08-12-2012

i can't use this software. can you help me?
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Xilinx Employee
Xilinx Employee
8,649 Views
Registered: ‎10-11-2007

We should probably ask what it is that the customer is concerned about. There is a lot of detail in the "bowls" of interconnect and input muxing which the customer wouldn't understand if we simply give them engineering style explanations. And they shouldn't really care about those anyway.

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Visitor
Visitor
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Registered: ‎08-12-2012


I wanted to know how is the relationship between SLR by the switch box. CLB are connected directly to the SLL or any other?
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Xilinx Employee
Xilinx Employee
8,638 Views
Registered: ‎10-11-2007

Is the question how SLRs interconnect and thus CLBs from one SLR are routed to CLBs on another SLR? Then the short answer is that SLLs do not connect directly to CLBs. SLLs do not span the entire SLRs, only the top/bottom reagions in a staggered fashion.  You can find information about how SLRs are interconnected in the below.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug872_largefpga.pdf

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Visitor
Visitor
8,635 Views
Registered: ‎08-12-2012

i see this document but i don't understand this part:
In Virtex-7 devices, each SLL component spans the vertical length of 50 interconnect tiles (equivalent to 50 Slice components). This is exactly the height of one clock region in Xilinx
7 series FPGA devices.
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Xilinx Employee
Xilinx Employee
8,633 Views
Registered: ‎10-11-2007

Why don't you send me an email and we can take this offline.

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Visitor
Visitor
8,630 Views
Registered: ‎08-12-2012

i don't have your email address
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Visitor
Visitor
8,615 Views
Registered: ‎08-12-2012

my email address is : ehsanfalahi@gmail.com
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Visitor
Visitor
6,343 Views
Registered: ‎08-12-2012

i want to know how SLRs are connected to each other with SLL clearly for routing in physical design. for example in 3d FPGA layers are connected by TSVs and 3d Switch box but i don't know in this device how SLRs are connected to each other. Can you send me a figure that show how SLRs connected to each other . and i want to know what is the role of switch matrix in this device because in FPGA editors show that vertical long lines are connected to this switch matrix but i don't know why?

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Visitor
Visitor
6,365 Views
Registered: ‎08-12-2012

i need to know details about thevirtex-7 's  architecture. who can help me?

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Moderator
Moderator
6,363 Views
Registered: ‎01-15-2008

Hi,

 

you can check the following link for most of the documents on Virtex-7 architecture details

http://www.xilinx.com/support/documentation/7_series_user_guides.htm

 

Regards

Krishna

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Visitor
Visitor
6,347 Views
Registered: ‎08-12-2012

i see this document but in this document i cannot find any details about architecture
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Scholar
Scholar
6,345 Views
Registered: ‎02-27-2008

There are many places to find architecture information,

 

Look at patents at the USPTO.

 

Look at papers published at conferences:

 

http://forums.xilinx.com/t5/PLD-Blog/The-25-Best-Papers-from-FPGA/ba-p/235040

 

along with papers on ACM, and IEEE.

 

Look at the Xilinx documentation.

 

Bascially, we have no interest in helping with your research:  you have to do it, all by yourself (no one will do it for you).  This presumes you are a student, and you have either chosen to do this, or was assigned it to do.

 

If this is a commercial application, a call to your local Xilinx Field Applications Engineer (FAE) will get all your questions answered.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
6,268 Views
Registered: ‎08-12-2012

Hi

 

my project is about developing a three dimensional physical design tool (TPR) based on SSI technology. thus for routing

and placement,  i need information about how to connect SLRs by SLLs that i cannot find it in Xilinx 's documentation.

who can help me?

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