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335 Views
Registered: ‎10-23-2018

Virtex7 FPGA Clocking

I want to generate a clock frequency of 2GHz in XC7VX485T-2 FFG1157 virtex7 FPGA. The resolution of this clock frequency should be 200KHz. I have studied the data sheet on 7 series clocking resources but I got confused with the MMCM/PLL input and output frequency ranges and VCO operating limitations. What should be the values of D,M and O while my reference clock is 125MHz?

Is there any way to generate such a fine resolution clock frequency?

 

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Moderator
Moderator
326 Views
Registered: ‎08-08-2017

Re: Virtex7 FPGA Clocking

Hi @azeemghauri278

 

MMCM_Foutmax and PLL_Foutmax  (MMCM and PLL Maximum output frequency ) for -2 speed grade Virtex-7T device is 933MHz . 2GHz is out of the specification and can not be generated by any combination of D, M and O.

 

Clocking Wizard IP will not allow you to set this.

Capture.PNG

 

 

 

If you manually instantiate MMCM or PLL primitive and set the D, M, O, you will get the DRC error saying unsupported configuration of D,M and O during Implementation.

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