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Contributor
Contributor
8,056 Views
Registered: ‎11-02-2015

Vitrex-7 series GTX transceiver configuration on vivado design suite

Hi,

 

I am new to FPGA. I am configuring  xc7vx485tffg1761-3 trnaceivers on vivado design suite.

 

After configuration the automatic verilog code (test bench and exedes) generated by the vivado tool has a signal called "data_out_i" and "error_count_i" , According to document (pg168, page number139) track_data_out_i should turn to state(logic) "1" and "error_count_i" should remain "0" than it is considered as a test configuration is passed or else it is failed. But the problem I am facing is after some amount of time "track_data_out_i" signal is changing its state to "x" (don't care) and all error_count signals too.

* I am transmitting and receiving signals on same transceiver. And then I did same thing with different combinations like transmitting from one transceiver and receiving at the other transceiver.



Please could anyone provide me a suggestion or soultion to this problem.

 

 

Thank you,

 

Shashank.

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Xilinx Employee
Xilinx Employee
8,043 Views
Registered: ‎02-16-2014

Hi @shashankupb

 

Can you attach your xci file here to check on this?

 

 

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Xilinx Employee
Xilinx Employee
8,031 Views
Registered: ‎02-06-2013

Hi

 

Generally you will see unknown states in simulation when there are multiple drivers.

 

Check for these in your modified 2 transceiver design.

 

 

Regards,

Satish

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Moderator
Moderator
8,023 Views
Registered: ‎02-16-2010

This looks like a test bench related issue if you have updated it to use two instances of example design top module.
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Contributor
Contributor
8,005 Views
Registered: ‎11-02-2015

Hi @pulim

 

Here I have attached xci file.

 

I would like to know know also, why should I need to do post sythesis and post implementation simulation, what is the main difference between these simulations? I went through asking google it says post implementation timing simulation is the nearest emulation why is it so? because I am getting this error in post implementation timing simulation. And also what is the significance of their functional simulations?

 

Thank you.

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Moderator
Moderator
7,996 Views
Registered: ‎02-16-2010

Please do not deviate the discussion in the current thread. You may ask this question through a different thread.

Have you checked any issues present with your testbench?

Whether the simulation work fine with example design from GT wizard?
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