11-02-2015 06:45 AM
I am new to FPGA. I am configuring xc7vx485tffg1761-3 trnaceivers on vivado design suite.
After configuration the automatic verilog code (test bench and exedes) generated by the vivado tool has a signal called "data_out_i" and "error_count_i" , According to document (pg168, page number139) track_data_out_i should turn to state(logic) "1" and "error_count_i" should remain "0" than it is considered as a test configuration is passed or else it is failed. But the problem I am facing is after some amount of time "track_data_out_i" signal is changing its state to "x" (don't care) and all error_count signals too.
* I am transmitting and receiving signals on same transceiver. And then I did same thing with different combinations like transmitting from one transceiver and receiving at the other transceiver.
Please could anyone provide me a suggestion or soultion to this problem.
11-02-2015 10:47 AM
Generally you will see unknown states in simulation when there are multiple drivers.
Check for these in your modified 2 transceiver design.
11-03-2015 10:04 AM
11-04-2015 08:26 AM
Here I have attached xci file.
I would like to know know also, why should I need to do post sythesis and post implementation simulation, what is the main difference between these simulations? I went through asking google it says post implementation timing simulation is the nearest emulation why is it so? because I am getting this error in post implementation timing simulation. And also what is the significance of their functional simulations?
11-04-2015 10:51 AM