cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
8,891 Views
Registered: ‎07-01-2014

[Vivado 12-1411]

Jump to solution

Vivado  

I use the kc705 to instantiate a 7 series Transceiver IP  , when i implement ,it has  two critical warnings ,as follows...

 

[Vivado 12-1411] Cannot set LOC property of ports, Terminal Q2_CLK1_GTREFCLK_PAD_N_IN has conflicting location from shape expansion (ILOGIC_X0Y174 FIXED, ILOGICE2.D2OBYP_SRC) vs original (IOB_X0Y173 FIXED, IOB33S.PAD) 
[Vivado 12-1411] Cannot set LOC property of ports, Terminal Q2_CLK1_GTREFCLK_PAD_N_IN has conflicting location from shape expansion (ILOGIC_X0Y174 FIXED, ILOGICE2.D2OBYP_SRC) vs original (IOB_X0Y173 FIXED, IOB33S.PAD)

 

however ,they are the same ...

 

what's the meaning of it???

 

In my XDC file ,i have this commend...

set_property LOC K29 [get_ports Q2_CLK1_GTREFCLK_PAD_N_IN ]
set_property LOC K28 [get_ports Q2_CLK1_GTREFCLK_PAD_P_IN ]

  K28,K29   is the pin of 156.25MHz.....

 

 

Meanwhile,this warning affect the bit file's generation ......

 

who can help me ???

 

thanks!!!

 

 

0 Kudos
Reply
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
11,947 Views
Registered: ‎02-06-2013

Hi

 

The user clocks generated by si570 cannot be used for the SFP+ transceiver,this clock is for FPGA logic.

 

Transceivers have dedicated clock pins and for KC705 the SFP+ is connected to QUAD117 and the reference clocks can be provided from the SMA connector or the SGMII clock.

 

The clock reference pins are G8 and G7.

 

Refer SGMII GTX transceiver clock generator section of UG810 to know more about this.

 

Also the pinout in the below link will give you clarity on the clock pins.

 

http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg900pkg.txt

 

 

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

0 Kudos
Reply
5 Replies
Xilinx Employee
Xilinx Employee
8,886 Views
Registered: ‎09-20-2012

Hi,

 

Can you open synthesized design and check how this port is connected in schematic "Q2_CLK1_GTREFCLK_PAD_N_IN "?

 

From the naming this looks like to be a GTREFCLK pin. If this is the case you need to lock them to the GT dedicated pins. 

 

K28 and K29 are not GT dedicated pins.

 

For more details refer to APPENDIX-A of http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Reply
Visitor
Visitor
8,875 Views
Registered: ‎07-01-2014

i want to connect  the gtx Ip with the SFP+ ,the reference clock is 156.25. Two way i can get this clock. In the KC705 board ,there is SMA interface which provides the clk ...another way ,through Si570 3.3V LVDS I2C Programmable Oscillator ,i can get this clk, K28 and K29  are the pin ....

 

thanks ...

 

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
11,948 Views
Registered: ‎02-06-2013

Hi

 

The user clocks generated by si570 cannot be used for the SFP+ transceiver,this clock is for FPGA logic.

 

Transceivers have dedicated clock pins and for KC705 the SFP+ is connected to QUAD117 and the reference clocks can be provided from the SMA connector or the SGMII clock.

 

The clock reference pins are G8 and G7.

 

Refer SGMII GTX transceiver clock generator section of UG810 to know more about this.

 

Also the pinout in the below link will give you clarity on the clock pins.

 

http://www.xilinx.com/support/packagefiles/k7packages/xc7k325tffg900pkg.txt

 

 

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

0 Kudos
Reply
Visitor
Visitor
8,864 Views
Registered: ‎07-01-2014

Thank u very much...

0 Kudos
Reply
Visitor
Visitor
8,646 Views
Registered: ‎07-03-2014

You can use 156.25 MHz reference clock from Si570 oscillator for SFP+ via K28 and K29 pins on KC705.

I had simillar problem with Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) and exactly same conflict messages.

I regenerated the core with "Include Shared Logic in example design" setting.

In generated IP Example Design I modified file with input clock buffers to use generic IBUFDS instead of IBUFDS_GTE2

Then I instantiated one of example HDL wrappers together with the generated core.

And now it works !

 

 

 

0 Kudos
Reply