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boomy
Visitor
Visitor
489 Views
Registered: ‎01-06-2020

Voltage drop for Clock output through SMA port

Hi

I'm using VCU108 board.

I want to make 'CLK_out' signal like drawing below.

boomy_0-1614868130629.png

 

The scheme is using inverter delay to make CLK_out signal.

The source of the CLK signal is used systemclk 300MHz and using clock wizard 

to make the clk 100MHz.

Finally for forward the signal come from 'counter module(The module I made to make CLK_out signal)' to output port VCU108 USER_SMA_CLOCK_N (AT14) pin using oddr ip block.

boomy_1-1614868130635.png

and pin constraints clk_out_0 signal like the code below

set_property PACKAGE_PIN AT14 [get_ports {clk_out_0}] 
set_property IOSTANDARD LVCMOS18 [get_ports {clk_out_0}] 

set_property PACKAGE_PIN AT14 [get_ports {clk_out_0}] set_property IOSTANDARD LVCMOS18 [get_ports {clk_out_0}]

I want clk_out signal has 1.8V voltage swing. 

But when observe this signal through VCU108 USER_SMA_CLOCK_N (AT14) pin

using oscilloscope

The Output Voltage Amplitude become 470mV.

boomy_2-1614868130720.png

 

 

Amplitude is too small.

For troubleshooting I insert 'BUFG' instantiation, but the result is same.

What is the problem for Voltage drop?

I need your help desperately...!

 

ps.this is my verilog code 

boomy_3-1614868130728.png

 

 

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6 Replies
drjohnsmith
Teacher
Teacher
473 Views
Registered: ‎07-09-2009

what delay do you think the buffer is giving to the signal ?

    what frequency of the output pulse do you expect to see ?

What is the data sheet speed clock to out of that pin your using ?

what is the bandwidth of the scope,  what cable are you using ?

  what sample speed do you have set on the scope ?

 

This is an asynchronous design, so how are you constraining your block such the you get an optimum signal route ?

What does the timing report show as the propagation delay of the output signal ?

 

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bruce_karaffa
Scholar
Scholar
450 Views
Registered: ‎06-21-2017

The inverter/XOR circuit you have drawn can be implemented in a single LUT.  The delay through a LUT is less than a nanosecond.  This means that you are asking the ODDR to toggle at a pulse width narrower than is was meant to.  You are trying to make a pulse with a width of less than an a nanosecond.  A single ended driver is a poor choice for this.  Also, any capacitance on the line will act as a low pass filter and lower the amplitude and widen the pulse.

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boomy
Visitor
Visitor
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Registered: ‎01-06-2020

sincerely, thanks for your reply. 

 

what delay do you think the buffer is giving to the signal ?

--> you mean buffer 'BUFG' that i gave? i thought BUFG do amplify the signal and reduce the clock's jitter

so i instantiate the BUFG for that reason.

 

what frequency of the output pulse do you expect to see ?

--> Expected pulse width of CLK_out is 0.5ns. and in implementation timing simulation 'not' gate propagation delay was 0.5ns so I used not gate.

 

what is the data sheet speed clock to out of that pin your using ?

--> SMA port can forward Maximum 9~10GHz speed.

 

what is the bandwidth of the scope,  what cable are you using ?

-->I'm using x1 cable so oscilloscope has no problem.

 

what sample speed do you have set on the scope ?

--> I have not check yet, but before I used same scope for years with same settings Maximum 800MHz.

 

After running Timing Implementation Simulation, it prints perfectly that I expected with 0.5ns not gate delay.

but in real world it has voltage drop.

So, I did another experiment for check whether design was wrong or the FPGA's original problem.

I use only one 'and' gate

because I want to see it is delay problem that I design or FPGA board's problem.

boomy_0-1614876735630.png

Drawing shows simplified result.

It also shows voltage drops.

I'm sorry for my poor explanation.

And again thanks for your reply!

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bruce_karaffa
Scholar
Scholar
430 Views
Registered: ‎06-21-2017

To accurately measure a low duty cycle, 0.5nS pulse you will need a scope with a bandwidth of several gigahertz.  10GHz is a nice number, but at least 5GHz.

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maps-mpls
Mentor
Mentor
424 Views
Registered: ‎06-20-2017

You need to consider everything everybody here is telling you, and think back to your systems and signals class as well as your circuit design 1 classes if you had them.  If your scope has a high bandwidth probe check its settings it may be doing some filtering internally. 


Recall, a LPF will add phase and also attenuate depending on the frequency content of your signal, and the frequency response of your overall signal path.

 

You will have impedance (R and C), and you are creating very short pulses, and attempting to measure them with a scope that has a limited bandwidth, additional probe capacitance, etc.  You might also configure your drive strength to be higher and your slew rate to be higher in your XDC file.

 

Make your pulse 20 nS long on a 1 MHz clock and all should be good on your scope.

*** Destination: Rapid design and development cycles ***
drjohnsmith
Teacher
Teacher
386 Views
Registered: ‎07-09-2009

So scope,

   to get a good representation of a pulse, you need to be getting at least 5 samples,

       if your expecting a 0.5 ns pulse, then you need at least 10 samples per ns,

 

Your 0.5 ns pulse, to get a good representations of the square edge, 

   you need to capture at least the 5th harmonic,

   your fundamental is 2 GHz, so you have a DC to 10 Ghz signal.

      This will need to be terminated a the scope to the cable / PCB impedance.

 

Now look at the rise / fall time of the logic you have selected for the output of the FPGA,

     I'd suggest that you have chosen a LVCMOS output, which has above a ns rise / fall time.

  If you want to run fast, you need to use one of the faster logic types of the FPGA such as LVDS 1.8 

This is differential, and has 200 mV swing, but it can toggle at sub ns speeds.

 

Bottom line, 

  a FPGA is not a good choice to make a sub ns pulse of any amplitude.

     You need to be looking at RF type constructions, using the PCB as the delay element, 

       and high speed RF transistors as your gate ,

You will alos be having to look at the PCB, FR4 is very sub optimal at these frequencies, you will be needing one of the Rodgers or such like RF PCB's.

just do a google, sub ns pulse generation was very popular a few years back as part of UWB radar designs, lots of published papers on how to do and not do it.

 

 

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