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Visitor odedyer
Visitor
2,663 Views
Registered: ‎09-04-2016

Weird timing issues when implementing on a specific PC

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Hi,

 

I have a design which generally has no  timing issues, but on a specific PC there's an endless number of paths (WNS -2.756, TNS -15,531.865...). Many of the paths are even between clock groups which I declared asynchronous in my XDC file (I see in the messages log that the XDC file is being read). On all other PCs the very same design passes with no issues.

Re-creating the project in a different folder doesn't help, while if re-creating the project in the exact same manner on a different PC there are no problems.

 

I think this started happening after I mistakenly assigned ports in my design to pins W7 and W8 (SMA_MGT_REFCLK_N and SMA_MGT_REFCLK_P) on the notorious PC, which of course caused errors during implementation. After re-assigning the ports to other pins there were no implementation errors, but the timing issues started.

 

Any idea what could be wrong?

 

Thanks!

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Xilinx Employee
Xilinx Employee
4,716 Views
Registered: ‎07-31-2012

Re: Weird timing issues when implementing on a specific PC

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Changing the PC should not affect your implementation results and especially the timing results. Please add the design filles afresh and try again and see if the timing errors are reproducible/not reproducible in both the PC's. Whenever you move the design around, try to re-generate all the cores from scrach and then try.

Furthehr what is the OS in the PC which fails?

If nothing helps and you still have these issues, please paste your design, timing reports from both the PC's so that we can check locally.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

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2 Replies
Xilinx Employee
Xilinx Employee
4,717 Views
Registered: ‎07-31-2012

Re: Weird timing issues when implementing on a specific PC

Jump to solution
Changing the PC should not affect your implementation results and especially the timing results. Please add the design filles afresh and try again and see if the timing errors are reproducible/not reproducible in both the PC's. Whenever you move the design around, try to re-generate all the cores from scrach and then try.

Furthehr what is the OS in the PC which fails?

If nothing helps and you still have these issues, please paste your design, timing reports from both the PC's so that we can check locally.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

Moderator
Moderator
2,607 Views
Registered: ‎01-16-2013

Re: Weird timing issues when implementing on a specific PC

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Hi,

 

Timing/Implementation results should not differ if the design/tool version/constraints and tool setting is consistent.

You can re-run the same design using same set of constraints and same tool settings, If issue reproduced again then 1st step is to go and compare the Synthesis and Implementation log. Check the checksum value for each phase and the value it is changed for the 1st time (did not match) is the root cause of different behavior.

I hope logs will give you the clarity on what's going wrong.

 

If you are unable to find the difference, please post the more details/log/project.

 

Thanks,
Yash