01-13-2017 09:38 AM
The LVDS standard in HR banks requires VCCO=2.5V. It is clean for me.
But if I connect two Artix-7 devices by differential lines and power both chips VCCO 1.8V.
What standard I should select to receive maximum performance?
In other words: is it possible to use IOSTANDARD=LVDS_25 on both sides, while Vcco will be 1.8V?
The link between similar Artix devices required, no other devices will be connected.
Could one estimate AC characteristics of this output (if it is possible at all)?
01-13-2017 09:51 AM
01-13-2017 10:31 AM
The HR IO must use 2.5 v for diff term to work (LVDS_25).
The HP IO must use 1.8 v for diff term to work (LVDS_18).
They will interface seemlessly (LVDS_25 to LVDS_18). But, with Vcco = 1.8 v on a HR bank, you cannot use LVDS_25.
Using a signal integrity simulator (I use Mentor Hyperlynx, and any Xilinx or distributor FAE can help you with that), you may examine all the possibilities. For example, LVCMOS_18 at 6 mA is about 50 ohms drive, so it matches pcb traces well. Using it with DDR (dual data rate with forwarded clock) it will be very fast as well (no resistors needed).
Its either that, or find a 2.5 v supply (to get LVDS_25).
01-16-2017 06:12 AM
Thank You for answer, Austin.
I should not select LVDS link for this design. I am not experienced in Hyperlynx, but I understand IBIS models and pcb simulation approach.
But for my curiosity, the LVDS driver in HR IO will not work from 1.8v by design or the performance of it will be out of specification?
01-16-2017 06:52 AM
It was not designed for that voltage, and yes, it would not meet specifications. It would function, but no way to tell if it would work. The next part would also be different.