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Visitor syemets_xil
Visitor
4,015 Views
Registered: ‎02-28-2013

What differential output for HR bank of Artix-7 with Vcco=1.8 will have maximum performance?

The LVDS standard in HR banks requires VCCO=2.5V. It is clean for me.

 

But if I connect two Artix-7 devices by differential lines and power both chips VCCO 1.8V.

What standard I should select to receive maximum performance?

 

In other words: is it possible to use IOSTANDARD=LVDS_25 on both sides, while Vcco will be 1.8V?

The link between similar Artix devices required, no other devices will be connected.

Could one estimate AC characteristics of this output (if it is possible at all)?

 

Thanks,

Sergey.

 

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Visitor syemets_xil
Visitor
4,010 Views
Registered: ‎02-28-2013

Re: What differential output for HR bank of Artix-7 with Vcco=1.8 will have maximum performance?

From table 17 of Artix-7 Datasheet (ds181) I can see that DIFF_HSTL_
II_18_F or DIFF_SSTL18 are good enough in timing. But due to lack of DCI in HR banks the external terminators are required. The purpose of not using 2.5V is to save pcb space. External resistors will wast significantly more space due to requirements of access top/bottom layers of the diff. pair.
Sergey.
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Scholar austin
Scholar
4,002 Views
Registered: ‎02-27-2008

Re: What differential output for HR bank of Artix-7 with Vcco=1.8 will have maximum performance?

Sergey,

 

The HR IO must use 2.5 v for diff term to work (LVDS_25).

 

The HP IO must use 1.8 v for diff term to work (LVDS_18).

 

They will interface seemlessly (LVDS_25 to LVDS_18).  But, with Vcco = 1.8 v on a HR bank, you cannot use LVDS_25.

 

Using a signal integrity simulator (I use Mentor Hyperlynx, and any Xilinx or distributor FAE can help you with that), you may examine all the possibilities.  For example, LVCMOS_18 at 6 mA is about 50 ohms drive, so it matches pcb traces well.  Using it with DDR (dual data rate with forwarded clock) it will be very fast as well (no resistors needed).

 

Its either that, or find a 2.5 v supply (to get LVDS_25).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor syemets_xil
Visitor
3,905 Views
Registered: ‎02-28-2013

Re: What differential output for HR bank of Artix-7 with Vcco=1.8 will have maximum performance?

Thank You for answer, Austin.
I should not select LVDS link for this design. I am not experienced in Hyperlynx, but I understand IBIS models and pcb simulation approach.

 

But for my curiosity, the LVDS driver in HR IO will not work from 1.8v by design or the performance of it will be out of specification?
BR,
Sergey Yemets.

 

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Scholar austin
Scholar
3,897 Views
Registered: ‎02-27-2008

Re: What differential output for HR bank of Artix-7 with Vcco=1.8 will have maximum performance?

SY,

 

It was not designed for that voltage, and yes, it would not meet specifications.  It would function, but no way to tell if it would work.  The next part would also be different.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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