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Explorer
Explorer
636 Views
Registered: ‎05-11-2015

What may happen if power-up sequence is not followed?

 

According to user guides, FPGA power sequence is to "minimize current draw and ensure I/Os are tri-stated". Are these the only risks?

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610 Views
Registered: ‎01-22-2015

@joancab 

According to user guides, FPGA power sequence is to "minimize current draw and ensure I/Os are tri-stated". Are these the only risks?

Specifications for "Power-On/Off Power Supply Sequencing" are given in the datasheet for your specific FPGA.  The issue of "minimize current draw and ensure I/Os are tri-stated" is always a concern.  However, with some devices there are more serious device reliability issues.  For example, the 7-Series devices have the following requirement (eg. see page 7 of DS182(v2.18)

The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.

Cheers,
Mark

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Explorer
Explorer
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Registered: ‎05-11-2015

 

In my case the alternative is to power up everything straight away, so that won't probably be a problem. Also because VCCO will not be above 2V5.

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556 Views
Registered: ‎01-22-2015

@joancab 

In my case the alternative is to power up everything straight away....

I can appreciate you wanting to keep things simple.  However, you must ensure that your power supplies have the extra current output necessary to support "powering up everything straight away".  How much extra current you say?  Well, I don't know and I haven't seen this in the Xilinx documents.

Sequencing power-up of the voltages is not that difficult.  Consider the TPS54318 switching supply with PWRGD and EN pins.  You can simple connect the PWRGD output from one TPS54318 to the EN of another TPS54318 to make their output voltages come up sequentially.  

Then, there is the choice of LDO vs switching-supply.  It may surprise you to know that a switching supply is preferred for reasons (soft-start and sequencing) described in the <this paper> from Texas Instruments.

Finally, Xilinx has partnered with other vendors to give you customized power solutions for FPGAs as described in <this link>. 

-enjoy the journey,
Mark

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Registered: ‎09-17-2018

As Mark notes,

There is no spec for all possible power-on sequences.  That said, if you design your power supply for any reasonable margin (most companies require at least 1.5X worst case current be able to be supplied, and many have 2X requirements) you should not have an issue.  On the other hand, if you are limited to a less than 1.2X supply, then you may find some units unable to power-on.

lowearthorbit

 

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Registered: ‎01-22-2015

@lowearthorbit   Thank you, Austin!

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Explorer
Explorer
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Registered: ‎05-11-2015

 

I know power sequencing is simple and there are off the shelf solutions. I always have implemented them without questioning these recommendations. 

What happens now is that a Zynq MPSoC has some 15 supplies, that can probably be bundled into 5 but, when sequencing, I will have to use pass transistors (because, for example, some 1V8 will have to power rail A first but rail B later on). The potential problem is I will have many of these supplies going through a single pass transistor in a remote environment with radiation. If that transistor fails, the rail fails, the SoC will probably fail and that's the end. I don't expect a trip with SpaceX and a soldering iron to replace a transistor.

An easy alternative is a separate supply for each rail. The problem here could be PCB space. Separate switchers are thermally a better option, imo.

tripled transistors in parallel would alleviate the risk one being open but the risk of one being permanently shorted gets tripled.

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Highlighted
408 Views
Registered: ‎09-17-2018

You do realize that MPSoC is not space-rated,

You should contact Xilinx.

lowearthorbit

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Explorer
Explorer
406 Views
Registered: ‎05-11-2015

 

We hope it's at least LEO rated, if not, we've been wasting three revolutions around the Sun

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Highlighted
297 Views
Registered: ‎09-17-2018

It isn't space rated,

So, hope you are lucky.,

lowearthorvit

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Explorer
Explorer
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Registered: ‎05-11-2015

 

You probably know that most, if not all, cubesat projects, expected to last for months to 1-2 years have COTS components including industrial-grade FPGAs

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