What timing constraints should be added in XDC for using Clocking Wizard to to divide the Kintex-7 FPGA differential clock sources (AD11, AD12)

[sourajitjash]

Hi,
I am using Kintex-7 FPGA. My design requires clock inout frequency = 50 MHz to meet post implementation timing requirements. As Kintex-7 has differential system Clock source of 200 MHz. So I am adding Clocking wizard (PLL) where sys_clk_p and sys_clk_n are inouts and clk_out is output (50 MHz). I want to know which things should be added for timing constraints in XDC file. Do I have to add the internal clocking wizard signals as _generated_clocks? Also should I have to define false_paths for them. Another question is whether I should add both of the differential clock inputs (sys_clk_p and sys_clk_n) in XDC? In one Answer=Record it is mentioned that only P side of the clock should be added. Please explain the timing constraint requirements to be added in XDC for using Clocking wizard (PLL). I am having timing violation while using Clocking Wizard (attached image). If I dont use the wizard, then I did not have post-implementation timing violation.

[arpansur]

Hi @sourajitjash,

Only P-side need to be constrained.

You are seeing inter clock path timing violation. If you think both the clock domains are asynchronous then you can use 

1. Either declare set_false_path for both the ways or
2. declare the clock paths as asynchronous

In case these clock domains are synchronous please apply proper multicycle path constraint.