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ackye
Contributor
Contributor
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Registered: ‎05-19-2020

When I configure the 7 series FPGA IO as DIFF_HSTL_II_F_18 to receive the SUBLVDS signal, do I need to add an additional 100 ohm termination resistor on the board?

When I configure the 7 series FPGA IO as DIFF_HSTL_II_F_18 to receive the SUBLVDS signal, do I need to add an additional 100 ohm termination resistor on the board?

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sandrao
Community Manager
Community Manager
301 Views
Registered: ‎08-08-2007

Hi @ackye 

 

I would suggest trying to go an IBIS simulation of your setup and following the suggestions in the SelectIO UG to ensure the correct thresholds are seen at the device.

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

Thanks,

Sandy


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