UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant rmelo@inti.gob.ar
Participant
3,440 Views
Registered: ‎04-26-2017

When to use IDELAY with a ISERDES?

Jump to solution

Hello. I suppose that maybe it is a very basic question, but I have read a lot of documents and I don't know why to use IDELAY in conjunction with ISERDES.

My case: I am developing an IP core to drive and ADC (ads42lb69 inside a fmc16x board from 4DSP) into a Zynq device. Each channel of the ADC is configured as 4 differential wires in QDR mode to obtain 16 bits per sample.

Vendor example: per each wire, an IODELAYE2 (in variable mode) and a ISERDESE2 is used.

Questions:
* Is the IODELAYE2 really needed? Why? (ISERDESE2 provide a not delayed input) Maybe to ensure sync between the four wires of the channel? (and I suppouse that if only a wire used, is really not needed?).
* If needed, why in variable mode? what about to use in fixed mode?

Probably the problem is that I don't know when IODELAY is needed.

Comments are welcomed :-D

Thanks.

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Historian
Historian
4,323 Views
Registered: ‎01-23-2009

Re: When to use IDELAY with a ISERDES?

Jump to solution

Presumably the ADC provides a clock along with the data. The ADC then guarantees some timing relationship between the clock and the data - something like "the data will be valid 0.5ns before the rising edge of the clock and remain valid for 0.5ns after the edge of the clock".

 

When this clock and data arrive at the FPGA, the FPGA uses the clock to sample the data. Depending on exactly how you bring the clock into the FPGA (and there are several clocking schemes), the FPGA will require a specific setup and hold time around the edges of the clock.

 

If the setup/hold requirement of the FPGA does not match the provided data valid window from the ADC, then you need to modify the setup/hold time of the FPGA so that it matches the data valid window from the FPGA. This, too, depending on the clocking scheme, can be done a number of different ways, but one way to do it is with the IDELAY; the IDELAY allows you to insert a programmable delay on a signal as it is entering the FPGA - you can delay either the clock or the data (or both).

 

Now, if the clocking scheme is adequate, and the data valid window of the ADC is "long enough" then you can use the IDELAY in static mode to insert "just the right amount of delay" to make the setup/hold requirement match the data vailid window of the ADC. However, the setup/hold time of the FPGA across all legal process, voltage and temperature variations is fairly large - in most technologies and speed grades (and clock architectures) larger than 1ns (and in some cases, even approaching 3ns). If the data valid window of the ADC is smaller than the best setup/hold window of the FPGA, then you cannot capture the data with static timing.

 

In this case, a dynamic calibration mechanism is needed to find the correct sampling point of the ADC. This can be done a number of ways, but one way is to use the IDELAY in dynamic mode, and adjust the delay setting with a state machine to find the ideal sampling point for the data.

 

Avrum

6 Replies
Historian
Historian
4,324 Views
Registered: ‎01-23-2009

Re: When to use IDELAY with a ISERDES?

Jump to solution

Presumably the ADC provides a clock along with the data. The ADC then guarantees some timing relationship between the clock and the data - something like "the data will be valid 0.5ns before the rising edge of the clock and remain valid for 0.5ns after the edge of the clock".

 

When this clock and data arrive at the FPGA, the FPGA uses the clock to sample the data. Depending on exactly how you bring the clock into the FPGA (and there are several clocking schemes), the FPGA will require a specific setup and hold time around the edges of the clock.

 

If the setup/hold requirement of the FPGA does not match the provided data valid window from the ADC, then you need to modify the setup/hold time of the FPGA so that it matches the data valid window from the FPGA. This, too, depending on the clocking scheme, can be done a number of different ways, but one way to do it is with the IDELAY; the IDELAY allows you to insert a programmable delay on a signal as it is entering the FPGA - you can delay either the clock or the data (or both).

 

Now, if the clocking scheme is adequate, and the data valid window of the ADC is "long enough" then you can use the IDELAY in static mode to insert "just the right amount of delay" to make the setup/hold requirement match the data vailid window of the ADC. However, the setup/hold time of the FPGA across all legal process, voltage and temperature variations is fairly large - in most technologies and speed grades (and clock architectures) larger than 1ns (and in some cases, even approaching 3ns). If the data valid window of the ADC is smaller than the best setup/hold window of the FPGA, then you cannot capture the data with static timing.

 

In this case, a dynamic calibration mechanism is needed to find the correct sampling point of the ADC. This can be done a number of ways, but one way is to use the IDELAY in dynamic mode, and adjust the delay setting with a state machine to find the ideal sampling point for the data.

 

Avrum

Highlighted
Participant rmelo@inti.gob.ar
Participant
3,394 Views
Registered: ‎04-26-2017

Re: When to use IDELAY with a ISERDES?

Jump to solution

Hello avrumw, thanks for the reply :-D

 

Yes, the ADC provides a clock along with data. The max sample frequency, which I want to use, is 250 MHz. Bit clock in QDR mode is 500 MHz and frame clock is 250 MHz. For bit clock, Ts min is 0.23 ns (0.31 ns typ) and Th min is 0.16 ns (0.29 ns typ). The datasheet says that the data clock edges are centered in the data valid window

 

The bit clock is entering in a MMCM to produce two clocks, 500 and 250 MHz, to feed idelay and iserdes.

 

If the setup/hold requirement of the FPGA does not match the provided data valid window from the ADC, then you need to modify the setup/hold time of the FPGA so that it matches the data valid window from the FPGA... the setup/hold time of the FPGA across all legal process, voltage and temperature variations is fairly large - in most technologies and speed grades (and clock architectures) larger than 1ns (and in some cases, even approaching 3ns). If the data valid window of the ADC is smaller than the best setup/hold window of the FPGA, then you cannot capture the data with static timing.

 

The data valid window, with a bit clock of 500 MHz is 2 ns... so I need to use idelay, right? with the dynamic calibration mechanism.

 

I assume that, based on the information that you provide, I need to use IDELAY in Variable mode. Please, let me know if seems rigth for you, based on my scenario.

 

Thanks a lot :-D

Tags (2)
0 Kudos
Historian
Historian
3,371 Views
Registered: ‎01-23-2009

Re: When to use IDELAY with a ISERDES?

Jump to solution

The data valid window, with a bit clock of 500 MHz is 2 ns... so I need to use idelay, right? with the dynamic calibration mechanism.

 

So, first, since you are saying that it is a "QDR" ADC, the data is transmitted at 500MHz DDR, not 500MHz SDR. If that is the case, then each data bit is present for 1ns, not 2ns. A window of 1ns is already too small static capture for pretty much all FPGA families in all speed grades.

 

Furthermore, the bit period (or unit interval - UI) is not the data valid window; the data valid window is only a portion of the UI. The specifications you gave tell us the data valid window; from 0.23ns before the clock edge to 0.16ns after (only the "min" matter - I still have no idea why manufacturers specify "typical" numbers - they are completely meaningless). So the actual size of the data window is 0.39ns. Furthermore, it is not perfectly "center aligned" (which makes things harder).

 

With this data window, not only is static capture completely impossible, you are even in the range where you are too fast for dynamic capture. Each family specifies the minimum window required for dynamic capture with the "perfect" dynamic capture mechanism; this is specified as Tsamp (for capture mechanisms that use the MMCM) or Tsamp_bufio (for capture mechanisms that use the BUFIO and the IDELAY). For the Kintex-7, as an example, Tsamp is significantly larger than 0.39 for all speedgrades, so using an MMCM based clocking mechanism won't work. The Tsamp_bufio is 0.30ns for the -3 speed grade only, and is greater than 0.39 for all other speed grades; so you have 0.01ns to play with. This has to account for the fact that the "perfect" dynamic calibration mechanism is hard to find, and you have the additional complexity of the clock being not perfectly centered in the data window. You also need to make allowance for clock jitter, for board routing delays, for signal integrity...

 

BUT - you need the MMCM to generate a 500MHz clock from the 250MHz, so you can't use the BUFIO. Therefore, you are stuck with Tsamp, which is larger than your data eye.

 

So, all told, if I have interpreted the numbers correctly, this interface is not possible in a 7-series. It may be possible in UltraScale using native capture, but I can't help you with this (I have never used it).

 

Avrum

Participant rmelo@inti.gob.ar
Participant
3,361 Views
Registered: ‎04-26-2017

Re: When to use IDELAY with a ISERDES?

Jump to solution

So, first, since you are saying that it is a "QDR" ADC, the data is transmitted at 500MHz DDR, not 500MHz SDR. If that is the case, then each data bit is present for 1ns, not 2ns.

 

Yes, you rigth.
 

So, all told, if I have interpreted the numbers correctly, this interface is not possible in a 7-series.

 

I have an example of the vendor, running in a Zynq 7045. Also, I have an example running in a Spartan 6. I will try to understand how is it used or at least, I will try to use the available code.

 

Thanks a lot for explanations.

0 Kudos
3,346 Views
Registered: ‎01-08-2012

Re: When to use IDELAY with a ISERDES?

Jump to solution

That ADC can be configured for DDR mode using SPI.  It will use twice as many pins for the interface, but the timing is much easier.  Perhaps the vendor's example did that?

 

Allan

Explorer
Explorer
1,385 Views
Registered: ‎07-17-2014

Re: When to use IDELAY with a ISERDES?

Jump to solution

Another item worth mentioning is that the IODELAY can help greatly with PCB layout length variations. 

I'm working on a design where we tried as best we could to control trace lengths between data channels for a 5-channel device, but the Zynq-020 we're using is made by someone else.
And while they list their trace delays... sometimes you never know how things will work out.

Using the IDELAY (in my case) takes out all the worry of trace lengths that might be off a little from each other and the clock input.

The IDELAY (and ODELAY) are really darn nice features (along with the dedicated SERDES modules).

0 Kudos